Wafer-level package and method for production thereof

Patent metadata

Field	Value
Publication number	US-9647196-B2
Application number	US-201214007074-A
Country	US
Kind code	B2
Filing date	Mar 28, 2012
Priority date	Apr 8, 2011
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A hermetic wafer-level package composed of two piezoelectric wafers, preferably identical in terms of material, and a production method therefor are presented. The electrical and mechanical connection between the two wafers is accomplished with frame structures and pillars, the partial structures of which, distributed between two wafers, are wafer-bonded with the aid of connecting layers.

First claim

The invention claimed is:

1. A wafer-level package for an electrical component comprising:
a first piezoelectric wafer comprising first component structures on a first surface;
a second piezoelectric wafer comprising second component structures;
a metallic frame structure connected to the first surface of the first wafer and a first surface of the second wafer such that a hermetically sealed cavity enclosed by the frame structure is formed between the first and second wafers;
electrical connections on a second surface of the second wafer that faces away from the cavity;
pillar-type electrical connections supported within the cavity on the first and second wafers and electrically connected to the first component structures and/or the second component structures;
contact pads within the cavity on the first surface of the first wafer and the first surface of the second wafer;
an irregular pattern of pillars arranged on a second surface of the first wafer, the second surface of the first wafer facing away from the first surface of the first wafer, wherein the irregular pattern of pillars is configured to dampen acoustic waves; and
a shielding layer formed over the pillars,
wherein the first component structures and the second component structures are enclosed within the cavity and are connected to the electrical connections via plated through-holes through the second wafer,
wherein all the plated through-holes end either on the frame structure, on a pillar connection or on a contact pad, without violating a hermeticity of the cavity,
wherein the frame structure, the pillar connections and the contact pads substantially consist of copper,
wherein the first component structures operate with surface acoustic waves and are embodied as an SAW filter, and
wherein the second component structures comprise transducers for surface acoustic waves and/or passive components selected from inductances and capacitances.

2. The wafer-level package according to claim 1 , wherein the shielding layer is configured to electrically or electromagnetically shield the first and second component structures.

3. The wafer-level package according to claim 1 , wherein the shielding layer comprises an Ni layer, and wherein the shielding layer is configured to electromagnetically shield the first and second component structures.

4. The wafer-level package according to claim 1 , wherein the shielding layer is connected via a plated through-hole through the first wafer to the first or second component structures, the frame structure or the electrical connections at the second surface of the second wafer.

5. The wafer-level package according to claim 1 , further comprising a damping layer for bulk waves, wherein the damping layer comprises the irregular pattern of the pillars, and wherein the damping layer comprises a thickness of a quarter wave (λ/4).

6. The wafer-level package according to claim 5 , wherein the pillars of the damping layer comprises Ni pillars embedded into a polymer matrix.

7. The wafer-level package according to claim 1 , further comprising a copper coil arranged on the first surface of the second wafer as one of the second component structures, wherein the copper coil is electrically conductively connected to the first component structures and/or the second component structures.

8. The wafer-level package according to claim 1 , wherein the pillar connections, as seen in a vertical direction, in each case have two sections having a different cross-sectional area per section.

9. The wafer-level package according to claim 1 ,
wherein the first wafer and/or the second wafer has transducers for surface acoustic waves as the component structures,
wherein each transducer has interdigitally arranged comb electrodes with electrode fingers,
wherein the electrode fingers of the comb electrodes are arranged at busbars and/or pads, and
wherein the pads are provided with a thickening composed of electrolytically deposited copper, the thickening being arranged above the pads or below the pads as a structure buried into the first and/or the second wafer.

10. The wafer-level package according to claim 1 , further comprising a stress reduction layer comprising a polymer arranged between the second surface of the second wafer and the electrical connections such that the stress reduction layer is located directly below the electrical connections.

11. The wafer-level package according to claim 1 , wherein the first and second piezoelectric wafers essentially consist of the same monocrystalline piezoelectric material, or constitute a combination of a wafer composed of lithium tantalate, lithium niobate or a wafer composed of quartz.

12. A wafer-level package for an electrical component comprising:
a first piezoelectric wafer comprising first component structures on a first surface;
a second piezoelectric wafer comprising second component structures;
a metallic frame structure connected to the first surface of the first wafer and a first surface of the second wafer such that a hermetically sealed cavity enclosed by the frame structure is formed between the first and second wafers;
electrical connections on a second surface of the second wafer that faces away from the cavity;
pillar-type electrical connections supported within the cavity on the first and second wafers and electrically connected to the first component structures and/or the second component structures;
contact pads within the cavity on the first surface of the first wafer and the first surface of the second wafer; and
a damping layer for bulk waves located on a second surface of the first wafer, the damping layer comprising a thickness of a quarter wave (λ/4), wherein the damping layer comprises an irregular pattern of pillars, wherein the pillars comprise Ni pillars embedded in a polymer matrix,
wherein the first component structures and the second component structures are enclosed within the cavity and are connected to the electrical connections via plated through-holes through the second wafer,
wherein all the plated through-holes end either on the frame structure, on a pillar connection or on a contact pad, without violating a hermeticity of the cavity,
wherein the frame structure, the pillar connections and the contact pads substantially consist of copper,
wherein the first component structures operate with surface acoustic waves and are embodied as an SAW filter, and
wherein the second component structures comprise transducers for surface acoustic waves and/or passive components selected from inductances and capacitances.

13. The wafer-level package according to claim 12 , wherein a copper coil is arranged on the first surface of the second wafer as one of the second component structures and is electrically conductively connected to the first component structures and/or the second component structures.

14. The wafer-level package according to claim 12 ,
wherein the first wafer and/or the second wafer has transducers for surface acoustic waves as the component structures,
wherein each transducer has interdigitally arranged comb electrodes with electrode fingers,
wherein the electrode fingers of the comb electrodes are arranged at busbars and/or pads, and
wherein the pads are provided with a thickening composed of electrolytically deposited copper, the thickening being arranged above the pads or below the pads as a structure buried into the first and/or the second wafer.

15. The wafer-level package according to claim 12 , further comprising a stress reduction layer comprising a polymer arranged between the second surface of the second wafer and the e

Assignees

• Bauer Christian
• Krueger Hans
• Portmann Juergen
• Stelzl Alois
• Pahl Wolfgang
• Koch Robert
• Snaptrack Inc

Inventors

• Bauer Christian
• Krueger Hans
• Portmann Juergen
• Stelzl Alois
• Pahl Wolfgang
• Koch Robert

Classifications

• H10W72/01225

  in solid form, e.g. by using a powder or by stud bumping · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H01L2224/1134

  Electricity · mapped topic

• H01L41/053 Primary

  Electricity · mapped topic

• B81C1/00301 Primary

  Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias · CPC title