Thin film transistor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9647141-B2
Application number	US-201615098385-A
Country	US
Kind code	B2
Filing date	Apr 14, 2016
Priority date	May 26, 2015
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

Embodiments of the present disclosure provide a thin film transistor (TFT) and a method of manufacturing the same, which enables to decrease the vertical resistance from the source and the drain to the polarity inversion region, so that the current from the source and the drain to the polarity inversion region may be increased, thereby improving the performances of the TFT. An active layer of the TFT is provided with a first groove and a second groove which neither pass through the active layer. A source and a drain of the TFT are formed at least partially in the first groove and the second groove, respectively. The source and the drain contact the active layer through the first groove and the second groove, respectively.

First claim

What is claimed is:

1. A thin film transistor, comprising:
a gate insulation layer, an active layer, a source and a drain, wherein
the active layer of the thin film transistor is provided with a first groove and a second groove which neither pass through the active layer, so that a vertical distance between a top surface of the gate insulation layer and a portion of a top surface of the active layer where the first groove and the second grove are formed, is less than a vertical distance between the top surface of the gate insulation layer and the other portion of the top surface of the active layer, the source and the drain of the thin film transistor are formed at least partially in the first groove and the second groove, respectively, and the source and the drain are in contact with the active layer through the first groove and the second groove, respectively.

2. The thin film transistor of claim 1 , wherein, the active layer is a metallic oxide semiconductor active layer, and
the thin film transistor further comprises an etch stop layer formed on the metallic oxide semiconductor active layer, wherein holes which pass through the etch stop layer are formed in a region of the etch stop layer that is in contact with the first groove and the second groove, and the source and the drain of the thin film transistor are in contact with the active layer through the respective holes as well as the first groove and the second groove, respectively.

3. The thin film transistor of claim 2 , wherein the grooves and the holes have circular cross sections, and a diameter of the groove is smaller than or equal to a diameter of the hole.

4. The thin film transistor of claim 1 , wherein a part of the active layer without the grooves has a thickness in a range of from 400 Å to 1000 Å.

5. The thin film transistor of claim 2 , wherein a part of the active layer without the grooves has a thickness in a range of from 400 Å to 1000 Å.

6. A thin film transistor array substrate comprising the thin film transistor of claim 1 .

7. A method of manufacturing a thin film transistor, wherein the method comprising:
forming a gate insulation layer and an active layer;
forming a first groove and a second groove in the active layer, wherein the first groove and the second groove neither pass through the active layer, so that a vertical distance between a top surface of the gate insulation layer and a portion of a top surface of the active layer where the first groove and the second grove are formed, is less than a vertical distance between the top surface of the gate insulation layer and the other portion of the top surface of the active layer; and
forming a source and a drain of the thin film transistor through a patterning process, wherein the source and the drain are formed at least partially in the first groove and the second groove, respectively, and are in contact with the active layer through the first groove and the second groove, respectively.

8. The method of claim 7 , further comprising:
forming an etch stop layer by deposition on the active layer in a case that the active layer is a metallic oxide semiconductor active layer; and
forming holes which pass through the etch stop layer in a region of the etch stop layer that is in contact with the first groove and the second groove, before forming the source and the drain of the thin film transistor through the patterning process;
wherein, the source and the drain are in contact with the active layer through the respective holes as well as the first groove and the second groove, respectively.

9. The method of claim 7 , wherein, the step of forming the first groove and the second groove in the active layer comprises:
coating a photoresist on a substrate on which an active layer film has been formed;
exposing the active layer film by employing an inductively coupled plasma (ICP) equipment and using a half tone mask (HTM) method and developing the exposed active layer film to form a photoresist fully reserved region, a photoresist partially reserved region and a photoresist fully removed region, wherein the photoresist fully reserved region corresponds to a region of the active layer without the grooves, the photoresist partially reserved region corresponds to a region of the first and second grooves, the photoresist fully removed region corresponds to a region of the active layer film excluding the region of the active layer without the grooves and the region of the first and second grooves;
fully removing a part of the active layer film in the photoresist fully removed region by using an etching process;
removing the photoresist in the photoresist partially reserved region by using an ashing process; and
peeling off the photoresist in the photoresist fully reserved region to expose the active layer.

10. The method of claim 8 , wherein, the step of forming the first groove and the second groove in the active layer, comprises:
coating a photoresist on a substrate on which an active layer film has been formed;
exposing the active layer film by employing an inductively coupled plasma (ICP) equipment and using a half tone mask (HTM) method and developing the exposed active layer film to form a photoresist fully reserved region, a photoresist partially reserved region and a photoresist fully removed region, wherein the photoresist fully reserved region corresponds to a region of the active layer without the grooves, the photoresist partially reserved region corresponds to a region of the first and second grooves, the photoresist fully removed region corresponds to a region of the active layer film excluding the region of the active layer without the grooves and the region of the first and second grooves;
fully removing a part of the active layer film in the photoresist fully removed region by using an etching process;
removing the photoresist in the photoresist partially reserved region by using an ashing process; and
peeling off the photoresist in the photoresist fully reserved region to expose the active layer.

11. The method of claim 8 , wherein, the step of forming the holes comprises:
forming the holes which pass through the etch stop layer in the region of the etch stop layer that is in contact with the first groove and the second groove by using an enhanced capacitive coupled plasma (ECCP) equipment,
wherein a diameter of the groove is smaller than or equal to a diameter of the hole.

12. The method of claim 7 , wherein a thickness of a part of the active layer without the grooves is in a range of from 400 Å to 1000 Å.

13. The method of claim 8 , wherein a thickness of a part of the active layer without the grooves is in a range of from 400 Å to 1000 Å.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optolectronics Tech Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Song Botao
• Jiang Tao
• Han Junhao
• Han Ling
• Cao Binbin
• Yang Chengshao

Classifications

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H01L29/7869

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic

• H01L27/127

  Electricity · mapped topic

• H01L29/78696 Primary

  Electricity · mapped topic