Low contact resistance thin film transistor

Patent metadata

Field	Value
Publication number	US-9647133-B2
Application number	US-201415036662-A
Country	US
Kind code	B2
Filing date	Nov 13, 2014
Priority date	Nov 15, 2013
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

The present invention relates to a novel thin film transistor (TFT) comprising a substrate ( 100 ) with a gate electrode layer ( 101 ) deposited and patterned thereon and a gate insulator layer ( 102 ) deposited on the gate electrode layer and the substrate, characterized in that the transistor further comprises (i) a carrier injection layer ( 103 ) arranged above the gate insulator layer, (ii) a source/drain (S/D) electrode layer ( 104 ) deposited on the carrier injection layer, and (iii) a semiconductor layer ( 106 ), methods for the production of such novel TFTs, devices comprising such TFTs, and to the use of such TFTs.

First claim

The invention claimed is:

1. A thin film transistor (TFT) comprising a substrate with a gate electrode layer deposited and patterned thereon and a gate insulator layer deposited on the gate electrode layer and the substrate, wherein the TFT further comprises (i) a carrier injection layer arranged above the gate insulator layer, (ii) a source/drain (S/D) electrode layer deposited on the carrier injection layer, and (iii) a semiconductor layer, wherein the TFT is patterned such that the semiconductor layer directly contacts the gate insulator layer, the carrier injection layer and the S/D electrode layer.

2. The TFT according to claim 1 , wherein the semiconductor layer is arranged above the carrier injection layer and the S/D electrode layer.

3. The TFT according to claim 1 , wherein the TFT is in Bottom Gate and Bottom Contact configuration.

4. The TFT according to claim 1 , wherein
the carrier injection layer is deposited on the gate insulator layer;
the TFT further comprises a protection layer, wherein the protection layer is deposited on the S/D electrode layer;
the TFT further comprises a protection layer, wherein the protection layer is deposited on the S/D electrode layer and the semiconductor layer is deposited and patterned on the protection layer;
the TFT further comprises a passivation layer, wherein the passivation layer is deposited on the semiconductor layer; and/or
the TFT further comprises a functionalization layer and a passivation layer, wherein the functionalization layer is deposited on the semiconductor layer and the passivation layer is deposited on the functionalization layer.

5. The TFT according to claim 1 , wherein the semiconductor layer directly contacts a) the gate insulator layer a side surface of the carrier injection layer, and c) a side surface of the S/D electrode layer.

6. The TFT according to claim 5 , wherein the contact of the semiconductor layer with the side surface of the S/D electrode layer occurs above the contact of the semiconductor layer with the side surface of the carrier injection layer.

7. The TFT according to claim 1 , wherein
the semiconductor layer is not located underneath the S/D electrode layer or the injection layer;
the semiconductor layer is in contact with the substrate averted surface of the S/D electrode layer or if the TFT comprises a protection layer the semiconductor layer is in contact with the substrate averted surface of the protection layer;
the TFT comprises a protection layer, wherein the protection layer is arranged above S/D electrode layer;
the TFT further comprises a protection layer, wherein the protection layer is arranged above S/D electrode layer and wherein the semiconductor layer reaches from the gate insulator layer to above the protection layer;
the TFT further comprises a pixel electrode; and/or
the TFT comprises a pair of injection layers which are horizontally positioned within the TFT with equal distance relative to the substrate layer and wherein the two injection layers are separated from each other by the semiconductor layer and wherein the TFT comprises a pair of S/D electrode layers which are horizontally positioned within the TFT with equal distance relative to the substrate layer and wherein the two S/D electrode layers are separated from each other by the semiconductor layer, and wherein the pair of S/D electrode layers is positioned above and in direct contact with the pair of injection layers.

8. The TFT according to claim 1 , wherein
the S/D electrode layer comprises a metal;
the S/D electrode layer has a thickness of 10 nm-1 μm;
the gate electrode layer comprises a metal;
the gate electrode layer has a thickness of 50 nm-500 nm;
the injection layer comprises a metal oxide conductor;
the injection layer has a thickness of 1 nm-200 nm;
the gate insulator layer comprises or consists of a metal oxide or -nitride or transition metal oxide or -nitride, or a polymeric material;
the gate insulator layer has a thickness of 10 nm-3 μm;
the substrate comprises glass, silicon, silicon dioxide, metal oxide, transition metal oxide, elementary metal or a polymeric material;
the substrate optionally has a thickness of 50 μm-0.7 mm;
the semiconductor layer comprises at least one metal oxide semiconductor selected from the group consisting of an indium, gallium, zinc, and tin oxide; and/or
the semiconductor layer has a thickness of 1-100 nm.

9. The TFT according to claim 1 , wherein
the S/D electrode layer consists essentially of at least one metal selected from the group consisting of Al, Mo, Cu, Ag and Nd;
the gate electrode layer consists essentially of at least one metal selected from the group consisting of Al, Mo, Cu, and Nd;
the injection layer essentially consists of at least one metal oxide conductor selected from the group consisting of ITO, AZO, GZO, ATO, ZTO, IZO, IGO, AZTO, HIZO, GTZO, GTO, and FTO;
the semiconductor layer consists essentially of at least one metal oxide semiconductor selected from the group consisting of IGZO, ITZO, ITO, GZO, ZTO, IZO, IGO, AZO, AZTO, HIZO, GTZO, GTO, tin oxide (SnO 2 ), gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), and zinc oxide (ZnO); and/or
the semiconductor layer further comprises nitrogen, fluorine, chlorine, and/or silicon.

10. The TFT according to claim 1 , wherein
the TFT further comprises a pixel electrode;
the protection layer comprises a metal oxide conductor, and/or a metal;
the protection layer has a thickness of 10 nm-500 nm;
the passivation layer comprises SiO x or SiN x , with x=0.1 to 3; and/or
the protection layer essentially consists of at least one metal oxide conductor selected from the group consisting of ITO, AZO, GZO, ATO, ZTO, IZO, IGO, AZTO, HIZO, GTZO, GTO, and FTO.

11. A method of manufacture of a TFT comprising:
providing a substrate;
depositing and patterning a gate electrode on the substrate;
depositing a gate insulator layer on the gate electrode and the substrate;
wherein the method further comprises
providing a carrier injection layer arranged above the gate insulator layer,
providing a S/D electrode layer deposited on the carrier injection layer, and
providing a semiconductor layer, wherein the TFT is patterned such that the semiconductor layer directly contacts the gate insulator layer, the carrier injection layer, and the S/D electrode layer.

12. The method according to claim 11 , wherein the semiconductor layer is arranged above the carrier injection layer and the S/D electrode layer.

13. The method according to claim 11 , wherein the TFT is in Bottom Gate and Bottom Contact configuration.

14. The method according to claim 11 , wherein
the provision of the carrier injection layer comprises depositing the carrier injection layer on the gate insulator layer;
the method further comprises providing a protection layer, wherein the protection layer is deposited on the S/D electrode layer;
the method further comprises providing a protection layer, wherein the protection layer is deposited on the S/D electrode layer and the semiconductor layer is deposited and patterned on the protection layer; and/or
the method further comprises providing a passivation layer, wherein the passivation layer is deposited on the semiconductor layer; and/or
the method further comprises providing a functionalization layer and a passivation layer, wherein the functionalization layer is deposited on the semiconductor layer and the passivation layer is deposited on the functionalization layer.

15. The method according to claim 11 , wherein the semiconductor layer is provided such that it directly contacts a) the

Assignees

• Pham Duy Vu
• Su Kuo Hui
• Evonik Degussa Gmbh

Inventors

• Pham Duy Vu
• Su Kuo Hui

Classifications

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title