Layout for LDMOS

Patent metadata

Field	Value
Publication number	US-9647110-B2
Application number	US-201514921999-A
Country	US
Kind code	B2
Filing date	Oct 23, 2015
Priority date	Oct 17, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A layout structure, a semiconductor device and an electronic apparatus are provided. The layout structure includes at least one LDMOS. The LDMOS includes a source, a drain and a gate. The drain is strip-shaped, the source and gate are cyclic structures, the inner circumference of the source is less than the outer circumference of the gate but is greater than the inner circumference of the gate, the inner ring of the source overlaps with the gate in all directions, and the drain is located inside the inner ring of the gate. Because the source and gate are configured as cyclic structures and the inner ring of the source overlaps with the gate in every direction, the layout structure can increase the current and reduce the area of LDMOS devices. Semiconductor devices manufactured based on the layout structure and electronic apparatuses including the semiconductor devices also have the above-described advantages.

First claim

What is claimed is:

1. A layout structure, comprising at least one laterally diffused metal oxide semiconductor (LDMOS), the at least one LDMOS including a source, a drain and a gate, wherein the drain is a strip-shaped structure, the source and the gate are cyclic structures, an inner circumference of the source is less than an outer circumference of the gate but is greater than an inner circumference of the gate, an inner ring of the source overlaps with the gate in all directions, and the drain is located inside the inner circumference of the gate and does not overlap an area defined by the inner circumference of the gate.

2. The layout structure of claim 1 , wherein the cyclic structure of the source includes a cyclic structure formed by a circle, an ellipse or a rectangle with a circle removed from a central region of the circle, the ellipse or the rectangle, or a cyclic structure formed by a rectangle with an ellipse removed from a central region of the rectangle.

3. The layout structure of claim 1 , wherein the cyclic structure of the gate includes a cyclic structure formed by a circle, an ellipse or a rectangle with a circle removed from a central region of the circle, the ellipse or the rectangle, or a cyclic structure formed by a rectangle with an ellipse removed from a central region of the rectangle.

4. The layout structure of claim 1 , wherein the strip-shaped structure of the drain includes a straight rectangle or a rounded rectangle.

5. The layout structure of claim 1 , wherein the layout structure includes at least two LDMOS devices, a body electrode located at the peripheral of the at least two LDMOS devices, and contact holes disposed on the source, the drain, the gate and the body electrode; and wherein only one row of contact holes is disposed in a neighboring region of adjacent LDMOS devices.

6. The layout structure of claim 5 , wherein the body electrode is a cyclic structure.

7. The layout structure of claim 5 , wherein the layout structure further includes a lumped body electrode disposed in the neighboring region of the adjacent LDMOS devices; and wherein at least one contact hole is disposed on the lumped body electrode.

8. A semiconductor device, comprising at least one laterally diffused metal oxide semiconductor (LDMOS), the at least one LDMOS including a source, a drain and a gate, wherein the drain is a strip-shaped structure in a plan view, the source and the gate are cyclic structures in the plan view, an inner circumference of the plan view of the source is less than an outer circumference of the plan view of the gate but is greater than an inner circumference of the plan view of the gate, an inner ring of the plan view of the source overlaps with the plan view of the gate in all directions in a horizontal plane, and the drain is located inside the inner circumference of the gate in the plan view and does not overlap an area defined by the inner circumference of the gate.

9. The semiconductor device of claim 8 , wherein the cyclic structure of the plan view of the source includes a cyclic structure formed by a circle, an ellipse or a rectangle with a circle removed from a central region of the circle, the ellipse or the rectangle, or a cyclic structure formed by a rectangle with an ellipse removed from a central region of the rectangle.

10. The semiconductor device of claim 8 , wherein the cyclic structure of the plan view of the gate includes a cyclic structure formed by a circle, an ellipse or a rectangle with a circle removed from a central region of the circle, the ellipse or the rectangle, or a cyclic structure formed by a rectangle with an ellipse removed from a central region of the rectangle.

11. The semiconductor device of claim 8 , wherein the strip-shaped structure of the plan view of the drain includes a straight rectangle or a rounded rectangle.

12. The semiconductor device of claim 8 , wherein the semiconductor device includes at least two LDMOS devices, a body electrode located at a peripheral of the at least two LDMOS devices, and contact holes disposed on the source, the drain, the gate and the body electrode; and wherein only one row of contact holes is disposed in a neighboring region of adjacent LDMOS devices.

13. The semiconductor device of claim 12 , wherein the plan view of the body electrode is a cyclic structure.

14. The semiconductor device of claim 12 , wherein the semiconductor device further includes a lumped body electrode disposed in the neighboring region of the adjacent LDMOS devices; and wherein at least one contact hole is disposed on the lumped body electrode.

15. An electronic apparatus, comprising:
a semiconductor device; and
electronic components coupled to the semiconductor device;
wherein the semiconductor device includes at least one LDMOS, the at least one LDMOS including a source, a drain and a gate, wherein the drain is a strip-shaped structure in a plan view, the source and the gate are cyclic structures in the plan view, an inner circumference of the plan view of the source is less than an outer circumference of the plan view of the gate but is greater than an inner circumference of the plan view of the gate, an inner ring of the plan view of the source overlaps with the plan view of the gate in all directions in a horizontal plane, and the drain is located inside the inner circumference of the gate in the plan view and does not overlap an area defined by the inner circumference of the gate.

16. The electronic apparatus of claim 15 , wherein the semiconductor device includes at least two LDMOS devices, a body electrode located at a peripheral of the at least two LDMOS devices, and contact holes disposed on the source, the drain, the gate and the body electrode; and wherein only one row of contact holes is disposed in a neighboring region of adjacent LDMOS devices.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Wang Haiqiang
• Cheng Yong
• Pu Xianyong

Classifications

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H01L29/7816

  Electricity · mapped topic

• H01L29/7823 Primary

  Electricity · mapped topic

• H01L29/41758

  Electricity · mapped topic

• H01L29/0696

  Electricity · mapped topic