Semiconductor device with modulated field element isolated from gate electrode

Patent metadata

Field	Value
Publication number	US-9647103-B2
Application number	US-94468207-A
Country	US
Kind code	B2
Filing date	Nov 26, 2007
Priority date	May 4, 2007
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

The current invention introduces a modulated field element incorporated into the semiconductor device outside the controlling electrode and active areas. This element changes its conductivity and/or dielectric properties depending on the electrical potentials of the interface or interfaces between the modulated field element and the semiconductor device and/or incident electromagnetic radiation. The element is either connected to only one terminal of the semiconductor device, or not connected to any terminal of a semiconductor device nor to its active area(s). Such an element can be used as modulated field plate, or a part of a field plate, as a passivation layer or its part, as a guard ring or its part, as a smart field or charge control element or its part, as a feedback element or its part, as a sensor element or its part, as an additional electrode or its part, as an electromagnetic signal path or its part, and/or for any other functions optimizing or modernizing device performance.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor channel;
source, drain, and gate electrodes, wherein the source electrode and drain electrode are located on opposing ends of the semiconductor channel and wherein the gate electrode is located on a gate dielectric layer between the source and drain electrodes and located above a surface side of a semiconductor structure forming the semiconductor channel; and
a modulated field element having at least one of: a variable conductivity or a variable dielectric property, wherein the modulated field element is positioned entirely within an opening between the gate and drain electrodes on the surface side of the semiconductor structure of the semiconductor device, wherein the opening is defined by an edge of the gate electrode closest to the drain electrode and an edge of the drain electrode closest to the gate electrode, wherein the modulated field element is physically and electrically isolated from the gate electrode, wherein a depletion region formed in the modulated field element extends from the gate electrode towards the drain electrode and varies in length based on a drain voltage bias, wherein the modulated field element comprises a doped semiconductor layer positioned between the gate dielectric layer and a passivation layer, wherein the gate dielectric layer extends beyond a perimeter of the gate electrode to cover all of a side surface of each of the doped semiconductor layer and the passivation layer and all of a top surface of the doped semiconductor layer, wherein the passivation layer comprises Si 3 N 4 , and wherein a material forming the passivation layer is distinct from a material forming the gate dielectric layer.

2. The semiconductor device of claim 1 , wherein the semiconductor device comprises a field effect transistor (FET).

3. The semiconductor device of claim 2 , wherein the FET comprises a heterostructure field effect transistor (HFET) or a high electron mobility field effect transistor (HEMT).

4. The semiconductor device of claim 1 , further comprising a field plate positioned on the gate dielectric layer.

5. The semiconductor device of claim 1 , wherein the modulated field element is further physically and electrically isolated from the drain electrode by a lateral trench.

6. The semiconductor device of claim 1 , wherein the doped semiconductor layer is selected from the group consisting of a semiconductor superlattice layer and a semiconductor p-n-p-n superlattice layer.

7. The semiconductor device of claim 1 , wherein the modulated field element is electrically connected to the drain electrode.

8. The semiconductor device of claim 1 , wherein the gate dielectric layer contacts a side portion of each of the source electrode and the drain electrode.

9. The semiconductor device of claim 1 , wherein the drain electrode covers all of another side surface of each of the doped semiconductor layer and the passivation layer.

10. The semiconductor device of claim 1 , wherein the doped semiconductor layer comprises one of an n-type doped amorphous silicon layer, poly-silicon, germanium, and compound semiconductor layers.

11. A heterostructure field effect transistor (HFET), comprising:
a modulated field element having a variable characteristic, wherein the modulated field element is located entirely within a gate-to-drain opening of the HFET defined by an edge of a gate electrode closest to a drain electrode, an edge of the drain electrode closest to the gate electrode, and a surface of a semiconductor structure forming a semiconductor channel of the HFET, and is adjacent to and immediately below a gate dielectric layer of a first material, and wherein the modulated field element comprises:
a doped semiconductor layer; and
a first dielectric layer adjacent to and immediately below the doped semiconductor layer, wherein the gate dielectric layer extends under the gate electrode beyond a perimeter thereof to cover all of a side surface of each of the doped semiconductor layer and the first dielectric layer and all of a top surface of the doped semiconductor layer, wherein the first dielectric layer is formed of a second material distinct from the first material, wherein the modulated field element is physically and electrically isolated from the gate electrode and is electrically connected to the drain electrode of the HFET, wherein the first dielectric layer comprises Si 3 N 4 , and wherein the doped semiconductor layer includes a depletion region having a depletion length that is dependent upon an applied gate-to-drain voltage.

12. The HFET of claim 11 , further comprising a field plate positioned on the gate dielectric layer.

13. The HFET of claim 11 , wherein the doped semiconductor layer is selected from the group consisting of a semiconductor superlattice layer and a semiconductor p-n-p-n superlattice layer.

14. The HFET of claim 11 , wherein the gate dielectric layer contacts a side portion of each of a source electrode and the drain electrode, and wherein the drain electrode covers all of another side surface of each of the doped semiconductor layer and the first dielectric layer.

15. A method for controlling a field distribution in an active area of a heterostructure field effect transistor (HFET), comprising:
providing a modulated field element positioned below a gate dielectric layer entirely within one of: a gate-to-drain opening or a gate-to-source opening above a surface a semiconductor structure forming a semiconductor channel of the HFET and having at least one variable characteristic, wherein the gate-to-drain opening or the gate-to-source opening is defined by an edge of a gate electrode closest to one of: a drain electrode or a source electrode, and an edge of the one of: the drain electrode or the source electrode closest to the gate electrode, wherein the modulated field element is physically and electrically isolated from the gate electrode located on the gate dielectric layer and is electrically connected to the one of: the drain electrode or the source electrode, wherein a depletion region formed in the modulated field element extends from the gate electrode towards the drain electrode and varies in length based on a drain voltage bias, wherein the modulated field element comprises a doped semiconductor layer positioned between the gate dielectric layer and a passivation layer, wherein the gate dielectric layer extends beyond a perimeter of the gate electrode to cover all of a side surface of each of the doped semiconductor layer and the passivation layer and all of a top surface of the doped semiconductor layer, wherein the passivation layer comprises Si 3 N 4 , and wherein a material forming the passivation layer is distinct from a material forming the gate dielectric layer; and
adjusting the at least one variable characteristic of the modulated field element to control the field distribution in the active area of the HFET.

16. The method of claim 15 , wherein the at least one variable characteristic is selected from the group consisting of a variable conductivity and a variable dielectric property.

17. The method of claim 15 , wherein the modulated field element is positioned within the gate-to-drain opening of the HFET and wherein the modulated field element is electrically connected to the drain electrode of the HFET.

18. The method of claim 15 , wherein the modulated field element is positioned within the gate-to-drain opening of the HFET, and wherein a dielectric property of the doped semiconductor layer is dependent upon at least one of: an applied g

Assignees

• Koudymov Alexei
• Shur Michael
• Gaska Remigijus
• Sensor Electronic Tech Inc

Inventors

• Koudymov Alexei
• Shur Michael
• Gaska Remigijus

Classifications

• H01L29/1606

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic

• H01L29/7786 Primary

  Electricity · mapped topic

• H01L29/4232

  Electricity · mapped topic

• H01L29/402

  Electricity · mapped topic