TFT array substrate and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9647012-B1
Application number	US-201615161260-A
Country	US
Kind code	B1
Filing date	May 22, 2016
Priority date	Jan 26, 2016
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

The present disclosure provides a TFT array substrate and manufacturing method thereof, forming a class structure of graphene-like two-dimensional layered semiconductor material on a base substrate and transferring the class structure of graphene-like two-dimensional layered semiconductor material on the designated position of the soft substrate to be a semiconductor active layer of the array substrate, therefore the semiconductor active layer of the TFT array substrate of the present disclosure uses a class structure of graphene-like two-dimensional layered semiconductor material to makes the array substrate having the advantage of higher electron mobility and mechanical property, excellent flexural resistance and reducing thickness of the substrate greatly.

First claim

What is claimed is:

1. A manufacturing method of a TFT array substrate, wherein the manufacturing method comprises:
providing a hard substrate;
providing a soft substrate, the soft substrate is arranged on the hard substrate;
a first insulating layer is formed on the soft substrate, wherein preset a designated position on the first insulating layer;
providing a base substrate;
a two-dimensional monolayer semiconductor material is formed on the base substrate, wherein the two-dimensional monolayer semiconductor material is MoS 2 ;
transferring the two-dimensional layered semiconductor material on the designated position;
hydrotreating the two-dimensional layered semiconductor material to form a semiconductor active layer;
wherein a thickness of the two-dimensional monolayer MoS 2 is 0.62 nm to 0.72 nm.

2. The manufacturing method according to claim 1 , wherein specific steps of the two-dimensional monolayer semiconductor material forming on the base substrate comprises:
forming a Mo pattern on the base substrate, the position of the Mo pattern is corresponding to the designated location;
using MoO 3 and material S at a temperature between 600 to 800 to form a two-dimensional monolayer MoS 2 on the Mo pattern by chemical vapor deposition.

3. The manufacturing method according to claim 2 , wherein a plane formed by the Mo atom in same layer of the two-dimensional monolayer MoS 2 is parallel with the soft substrate.

4. The manufacturing method according to claim 1 , wherein after the step of providing a soft substrate and before the step of forming a first insulating layer on the soft substrate, further comprises:
a first gate electrode is formed on the soft substrate, wherein the first insulating layer covers the first gate electrode and protrudes on the soft substrate, and the position of the first gate electrode corresponds to the designated position.

5. The manufacturing method according to claim 4 , wherein after the step of hydrotreating the two-dimensional monolayer semiconductor material to form a semiconductor active layer, further comprises:
Further formed a source electrode and a drain electrode on the first insulating layer by mask process, wherein the source electrode and the drain electrode are arranged at intervals by the semiconductor active layer, and the source electrode and the drain electrode contact the semiconductor active layer respectively.

6. The manufacturing method according to claim 1 , wherein after the step of hydrotreating the two-dimensional monolayer semiconductor material to form a semiconductor active layer, further comprises:
Further formed a source electrode and a drain electrode on the first insulating layer by mask process, the source electrode and the drain electrode are arranged at intervals by the semiconductor active layer and the source electrode and the drain electrode contact the semiconductor active layer respectively;
arranging a second insulating layer on the source electrode, the drain electrode and the semiconductor active layer;
forming a second gate electrode on the second insulating layer, wherein the position of the second gate electrode corresponds to the position of the semiconductor active layer.

7. A TFT array substrate, wherein the array substrate comprises:
a hard substrate;
a soft substrate, the soft substrate is arranged on the hard substrate;
a first insulating layer, the first insulating layer is arranged on the soft substrate;
a semiconductor active layer, the semiconductor active layer is arranged on a pre-specified location of the first insulating layer, and the semiconductor active layer is a two-dimensional monolayer semiconductor material with a thickness of 0.62 nm to 0.72 nm, wherein the two-dimensional monolayer semiconductor material is MoS 2 .

8. The array substrate according to claim 7 , wherein the array substrate further comprises:
a first gate electrode, the first gate electrode is arranged between the soft substrate and the first insulating layer, and the first gate electrode corresponds to the semiconductor active layer;
a source electrode and a drain electrode, the source electrode and the drain electrode are arranged at intervals on the first insulating layer by the semiconductor active layer, and the source electrode and the drain electrode contact the semiconductor active layer respectively.

9. The array substrate according to claim 7 , wherein the array substrate further comprises:
a source electrode and a drain electrode, the source electrode and the drain electrode are arranged at intervals on the first insulating layer by the semiconductor active layer, and the source electrode and the drain electrode contact the semiconductor active layer respectively;
a second insulating layer, the second insulating layer covers on the semiconductor active layer, the source electrode and the drain electrode;
a second gate electrode, the second gate electrode is arranged on the second insulating layer, and the position of the second gate electrode corresponds to the position of the semiconductor active layer.

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd
• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Liang Bo

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H01L27/127 Primary

  Electricity · mapped topic

• H01L29/41733

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic

• H01L29/42384

  Electricity · mapped topic