Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9646983-B2
Application number	US-201514963739-A
Country	US
Kind code	B2
Filing date	Dec 9, 2015
Priority date	Dec 19, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location. To form the plurality of line patterns including the at least two continuous line repetition units, a plurality of reference patterns are formed repeatedly at a uniform reference pitch on a feature layer. A plurality of first spacers covering both side walls of each of the plurality of reference patterns are formed. A plurality of second spacers covering both side walls of each of the plurality of first spacers are formed by removing the plurality of reference patterns. The feature layer is etched using the plurality of second spacers as an etch mask by removing the plurality of first spacers.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of line patterns formed on a substrate,
wherein the plurality of line patterns comprise at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location, wherein the at least two line repetition units have a same width, and continuously arranged in the first direction,
wherein widths of the plurality of line patterns are defined by a plurality of spaces disposed between the plurality of line patterns,
wherein the plurality of spaces comprise at least two continuous space repetition units having, as one space repetition unit, four spaces continuously arranged in the first direction and having variable widths based on location, and
wherein the at least two space repetition units have a same width.

2. The semiconductor device of claim 1 , wherein the one of the line repetition units included in the plurality of line patterns comprises:
a first line pattern having a first width in the first direction;
a second line pattern adjacent to the first line pattern and having a second width greater than the first width in the first direction;
a third line pattern adjacent to the second line pattern and having a third width greater than the first width in the first direction; and
a fourth line pattern adjacent to the third line pattern and having a fourth width smaller than the third width in the first direction.

3. The semiconductor device of claim 2 , wherein the second width and the third width have a same size.

4. The semiconductor device of claim 2 , wherein the first width and the fourth width have a same size.

5. The semiconductor device of claim 1 , wherein one of the space repetition units included in the plurality of spaces comprises:
a first space having a fifth width in the first direction;
a second space adjacent to the first space and having a sixth width greater than the fifth width in the first direction;
a third space adjacent to the second space and having a seventh width smaller than the sixth width in the first direction; and
a fourth space adjacent to the third space and having an eighth width greater than the seventh width in the first direction.

6. The semiconductor device of claim 5 , wherein the fifth width and the seventh width have a same size.

7. The semiconductor device of claim 5 , wherein the sixth width and the eighth width have a same size.

8. The semiconductor device of claim 5 , wherein the first width and the fifth width have a same size.

9. A semiconductor device comprising:
a plurality of device isolation regions defining a plurality of active regions in a plurality of line shapes extending in parallel to each other on a substrate,
wherein the plurality of active regions comprise at least two continuous active region repetition units having, as one of the active region repetition units, four active regions continuously arranged in a first direction and having variable widths based on location,
wherein the at least two active region repetition units have a same width, and continuously arranged in the first direction,
wherein the plurality of active regions and the plurality of device isolation regions are alternately arranged in the first direction,
wherein the plurality of device isolation regions comprise at least two continuous device isolation region repetition units having, as one of the device isolation region repetition units, four device isolation regions continuously arranged in the first direction and having variable widths based on location, and
wherein the at least two device isolation region repetition units have a same width.

10. The semiconductor device of claim 9 , wherein the one of the active region repetition units comprises:
a first active region having a first width in the first direction;
a second active region adjacent to the first active region and having a second width greater than the first width in the first direction;
a third active region adjacent to the second active region and having a third width greater than the first width in the first direction; and
a fourth active region adjacent to the third active region and having a fourth width smaller than the third width in the first direction.

11. The semiconductor device of claim 10 , wherein the second width and the third width have a same size.

12. The semiconductor device of claim 10 , wherein the first width and the fourth width have a same size.

13. The semiconductor device of claim 9 , wherein the plurality of device isolation regions comprise a plurality of device isolation air gaps each disposed in each of the plurality of device isolation regions,
wherein the plurality of device isolation air gaps comprise at least two continuous device isolation air gap repetition units having four device isolation air gaps continuously arranged in the first direction and having variable widths based on location as one device isolation air gap repetition unit.

14. A semiconductor device comprising:
a plurality of line patterns formed on a substrate;
wherein the plurality of line patterns define a plurality of spaces disposed therebetween, the plurality of spaces comprising at least two continuous space repetition units having; as one of the space repetition units, four spaces continuously arranged in a first direction and having variable widths based on location; and
wherein the at least two space repetition units have a same width and continuously arranged in the first direction.

15. The semiconductor device of claim 14 , wherein one of the space repetition units included in the plurality of spaces comprises:
a first space having a first width in the first direction;
a second space adjacent to the first space and having a second width greater than the first width in the first direction;
a third space adjacent to the second space and having a third width smaller than the second width in the first direction; and
a fourth space adjacent to the third space and having a fourth width greater than the third width in the first direction.

16. The semiconductor device of claim 15 , wherein the first width and the third width have a same size.

17. The semiconductor device of claim 15 , wherein the second width and the fourth width have a same size.

18. The semiconductor device of claim 14 , wherein the plurality of line patterns comprise at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location.

Assignees

• Yun Jang-Gn
• Lim Joon Sung
• Ahn Jae-Ho
• Samsung Electronics Co Ltd

Inventors

• Yun Jang-Gn
• Lim Joon Sung
• Ahn Jae-Ho

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H01L29/0653

  Electricity · mapped topic

• H01L27/11565 Primary

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic