Methods of forming buried vertical capacitors and structures formed thereby

Patent metadata

Field	Value
Publication number	US-9646972-B2
Application number	US-201314912402-A
Country	US
Kind code	B2
Filing date	Sep 25, 2013
Priority date	Sep 25, 2013
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure.

First claim

What is claimed is:

1. A method of forming a structure comprising:
forming at least one opening in a substrate, wherein the substrate does not comprise transistors;
forming a conductive material in the opening;
forming an insulator material on the conductive material and on the substrate;
forming a device layer on the insulator material on the conductive material and on the insulator material on the substrate; and
forming a contact through the insulator material to connect the conductive material to a device disposed in the device layer.

2. The method of claim 1 further comprising wherein the opening comprises a depth of at least about 5 microns.

3. The method of claim 1 further comprising wherein the substrate comprises a bulk silicon region and is disposed below the device layer.

4. The method of claim 1 further comprising wherein a dielectric material is formed to line the conductive material, wherein the dielectric material is disposed between the substrate and the conductive material.

5. The method of claim 1 further comprising wherein the device layer is formed using one of a layer transfer process and a thin film process.

6. The method of claim 1 further comprising forming a resistor material in the substrate adjacent the conductive material.

7. The method of claim 1 further comprising wherein the conductive material comprises a portion of a vertical capacitor structure.

8. The method of claim 1 further comprising wherein the openings are filled with a doped dielectric, wherein the doped dielectric is annealed and dopes the substrate.

9. The method of claim 7 further comprising wherein the vertical capacitor structure further comprises alternating layers of the conductive material and the dielectric material.

10. A method of forming a structure comprising:
forming a plurality of capacitor structures in a substrate, wherein each of the capacitor structures are vertically disposed in a corresponding trench within the substrate, wherein each of the capacitor structures includes a conductive material, and wherein the conductive material of at least two adjacent capacitor structures are physically joined;
forming an insulator layer on a top surface of the capacitor structures;
forming a device layer on the insulator layer; and
forming a contact to couple a device disposed in the device layer to at least one of the capacitor structures.

11. The method of claim 10 further comprising forming an array of the capacitor structures in the substrate.

12. The method of claim 10 further comprising wherein the contact is formed adjacent a transistor device disposed in the device layer and contacts the at least one capacitor structure through the insulator layer.

13. The method of claim 10 further comprising wherein the contact is formed adjacent a transistor device disposed in the device layer and contacts a region of the substrate adjacent at least one capacitor.

14. The method of claim 10 further comprising wherein the contact comprises a counter electrode for a common ground plane.

15. The method of claim 10 further comprising wherein the substrate comprises a portion of a SOI device, and wherein the substrate does not comprise transistors.

16. A structure comprising:
a plurality of capacitor structures disposed in a substrate, wherein each of the capacitor structures are vertically disposed in a corresponding trench within the substrate and wherein each of the capacitor structures comprises a conductive material disposed vertically in the substrate and a dielectric material lining a portion of the conductive material and wherein the conductive material of at least two adjacent capacitor structures are physically joined;
an insulator layer disposed on a top surface of the capacitor structures;
a device layer disposed on the insulator layer; and
a contact disposed through the insulator material, wherein the contact couples a device in the device layer with at least one of the capacitor structures.

17. The structure of claim 16 further comprising wherein the contact is adjacent a transistor disposed in the device layer, and directly contacts a top portion of a conductive material of the at lease one capacitor structure.

18. The structure of claim 16 further comprising wherein the at least one capacitor structure comprises a depth of greater than about 5 microns.

19. The structure of claim 16 further comprising wherein the device layer comprises at least one transistor device.

20. The structure of claim 16 further comprising a resistor structure disposed in the substrate and adjacent the at least one capacitor structure.

21. The structure of claim 16 further comprising wherein one end of the contact is disposed adjacent the transistor, and another end of the contact is disposed adjacent the at least one capacitor structure on a portion of the substrate.

22. The structure of claim 16 further comprising a system comprising:
a bus communicatively coupled to the structure; and
an eDRAM communicatively coupled to the bus.

Assignees

• Baskaran Rajashree
• Jun Kimin
• Morrow Patrick
• Intel Corp

Inventors

• Baskaran Rajashree
• Jun Kimin
• Morrow Patrick

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/212

  of only capacitors · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H01L27/1087

  Electricity · mapped topic

• H01L27/0629

  Electricity · mapped topic