Packaging mechanisms for dies with different sizes of connectors

Patent metadata

Field	Value
Publication number	US-9646894-B2
Application number	US-201313922023-A
Country	US
Kind code	B2
Filing date	Jun 19, 2013
Priority date	Mar 15, 2013
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate. The usage of the interconnect substrate enables cost reduction because it is cheaper to make than an interposer with through silicon vias (TSVs). The interconnect substrate also enables dies with different sizes of bump structures to be packaged in the same die package.

First claim

What is claimed is:

1. A semiconductor die package, comprising:
a first packaged die;
a second packaged die;
an interconnect substrate having a first side, a second side opposite the first side, and a sidewall extending between the first side and the second side, wherein the interconnect substrate comprises a redistribution structure on the first side, wherein the second side of the interconnect substrate is free from connectors, and wherein the first packaged die and the second packaged die are bonded to the first side of the redistribution structure; and
a package substrate with an interconnect structure, the package substrate having a recess, wherein the interconnect substrate is bonded to a bottom surface of the recess, wherein the second side of the interconnect substrate faces the bottom surface of the recess, wherein the sidewall of the interconnect substrate extends into the recess, wherein the sidewall of the interconnect substrate faces a sidewall of the recess, wherein the package substrate is electrically connected to the interconnect substrate using a conductive connector, wherein the conductive connector physically contacts the sidewall of the interconnect substrate and the sidewall of the recess, wherein the first packaged die and the second packaged die are electrically connected to the interconnect substrate and wherein the first packaged die is directly bonded to the package substrate.

2. The semiconductor die package of claim 1 , wherein the first packaged die has a plurality of first connectors with a first width and a plurality of second connectors with a second width, and wherein the first width is larger than the second width, and wherein the plurality of first connectors are bonded to bonding structures of the package substrate, and wherein the plurality of second connectors are bonded to the interconnect substrate.

3. The semiconductor die package of claim 2 , wherein the first width is in a range from about 60 μm to about 300 μm and the second width is in a range from about 10 μm to about 60 μm.

4. The semiconductor die package of claim 1 , wherein the interconnect substrate has contact structures to make electrical contact with the interconnect structure of the package substrate.

5. The semiconductor die package of claim 4 , wherein the contact structures are located at edges of the interconnect substrate.

6. The semiconductor die package of claim 1 , wherein the first packaged die is a processing unit and the second packaged die is a memory device.

7. The semiconductor die package of claim 1 , further comprising a molding compound encapsulating the first package die and the second packaged die, wherein no portion of the molding compound is interposed between the interconnect substrate and the package substrate.

8. The semiconductor die package of claim 1 , wherein the second side of the interconnect substrate physically contacts a top surface of the package substrate.

9. A semiconductor die package, comprising:
a package substrate;
an interconnect substrate mounted to the package substrate, the interconnect substrate having a redistribution layer thereon, a bottom surface of the interconnect substrate physically contacting a top surface of the package substrate, the bottom surface of the interconnect substrate being free from connectors, wherein the interconnect substrate is mounted within a cavity formed in the package substrate;
an electrical connector physically contacting a sidewall of the interconnect substrate;
a first packaged die electrically bonded to the interconnect substrate through a first μ-bump connection and electrically bonded to the package substrate through a second connection other than a μ-bump connection, the second connection physically contacting the first packaged die and the package substrate; and
a second packaged die electrically bonded to the package substrate through a second μ-bump connection.

10. The semiconductor die package of claim 9 , wherein the electrical connector physically contacting the sidewall of the interconnect substrate is solder ball.

11. The semiconductor die package of claim 9 , wherein a topmost surface of the interconnect substrate is substantially planar with a topmost surface of the package substrate.

12. The semiconductor die package of claim 9 , further comprising a molding compound encapsulating the first package die and the second packaged die, at least a portion of the molding compound extending into the cavity.

13. The semiconductor die package of claim 9 , wherein the electrical connector physically contacts a sidewall of the cavity, and wherein the sidewall of the cavity faces the sidewall of the interconnect substrate.

14. The semiconductor die package of claim 9 , wherein the sidewall of the cavity is spaced apart from the sidewall of the interconnect substrate.

15. A packaged device comprising:
a package substrate;
an interconnect substrate mounted to the package substrate and electrically connected to the package substrate by an interconnect connection, a bottom surface of the interconnect substrate facing a top surface of the package substrate, and the interconnect connection physically contacting a sidewall of the interconnect substrate;
a first packaged die electrically connected to the interconnect substrate by at least one μ-bump connection and directly bonded to the package substrate by at least one other connection;
a second packaged die, adjacent the first packaged die, electrically connected to the interconnect substrate by at least one μ-bump connection; and
a molding compound encapsulating the first package die and the second packaged die and encapsulating the interconnect connection.

16. The packaged device of claim 15 , wherein the at least one other connection is not a μ-bump connection.

17. The packaged device of claim 15 , wherein the interconnect substrate is mounted in an opening within the package substrate.

18. The packaged device of claim 15 , wherein the bottom surface of the interconnect substrate is free from connectors.

19. The packaged device of claim 17 , wherein the bottom surface of the interconnect substrate physically contacts a bottom surface of the opening.

20. The packaged device of claim 17 , wherein the interconnect connection physically contacts a sidewall of the opening.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chih-Hua
• Chen Chen-Shien
• Hsiao Ching-Wen

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W90/722

  between stacked chips · CPC title