Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices

Patent metadata

Field	Value
Publication number	US-9646869-B2
Application number	US-71574310-A
Country	US
Kind code	B2
Filing date	Mar 2, 2010
Priority date	Mar 2, 2010
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator material, at least one diode comprising a single crystalline silicon material over a conductive material, and a memory cell on the at least one diode. The at least one diode may be formed from a single crystalline silicon material. Methods of forming such semiconductor devices are also disclosed.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first semiconductor substrate;
a second semiconductor substrate over and bonded to the first semiconductor substrate;
a conductive material of the second semiconductor substrate being over an insulator material comprised by the first semiconductor substrate in a bonded structure, the bonded structure having an amorphous adhesive material between and contacting the insulator material and the conductive material, the amorphous adhesive material comprising one or both of amorphous silicon and amorphous germanium, the amorphous adhesive material and the conductive material being patterned;
at least one diode comprising a single crystalline silicon material over the conductive material, the at least one diode comprising a first doped region overlying the conductive material and a second doped region overlying the first doped region, wherein a conductivity of the first doped region is opposite a conductivity of the second doped region; and
a memory cell over the second doped region; the memory cell comprising a bottom electrode, a memory medium, and a top electrode; the top electrode being a bit line in contact with the memory medium without electrically coupling to any separate top electrode material between the bit line and the memory medium.

2. The semiconductor device of claim 1 , wherein the first doped region comprises an N-type doped region and the second doped region comprises a P-type doped region.

3. The semiconductor device of claim 1 , wherein the first doped region comprises a P-type doped region and the second doped region comprises an N-type doped region.

4. The semiconductor device of claim 1 , wherein the at least one diode has a width of less than about 20 nm.

5. The semiconductor device of claim 1 , wherein the at least one diode has an aspect ratio of less than about 20:1.

6. A semiconductor device, comprising:
a first semiconductor substrate comprising an insulative material over a semiconductive material;
a second semiconductor substrate over and bonded to the first semiconductor substrate, the second substrate having a conductive material and an adhesive material over the conductive material, the adhesive material comprising one or both of amorphous silicon and amorphous germanium, being distinct from the insulative material and being over and contacting the insulative material of the first substrate in the bonded structure, the second substrate being patterned such that trenches extend through all materials comprised by the second substrate, a base surface of each trench being an upper surface of the insulative material comprised by the first substrate;
at least one diode comprising a single crystalline silicon material over the conductive material in the bonded structure, the at least one diode comprising a first doped region overlying the conductive material and a second doped region overlying the first doped region, wherein a conductivity of the first doped region is opposite a conductivity of the second doped region; and
a memory cell over the second doped region.

7. The semiconductor device of claim 6 , wherein the adhesion material comprises amorphous silicon.

8. The semiconductor device of claim 6 , wherein the adhesion material comprises amorphous germanium.

9. A semiconductor device comprising:
an insulator material on a first semiconductor substrate;
a word line structure adhered to the insulator material, the word line structure comprising a patterned amorphous adhesion material comprising one or both of amorphous silicon and amorphous germanium contacting the insulator material, and conductive material contacting the adhesion material, the conductive material being on a second substrate, the first and second substrates being bonded to one another by the adhesion material;
at least one diode on the conductive material, the adhesion material and the conductive material forming a longitudinally coextensive strap portion extending laterally beyond each of opposing lateral edges of the diode; and
a memory cell on the at least one diode.

10. The semiconductor device of claim 9 , further comprising a logic device formed on the first semiconductor substrate.

11. The semiconductor device of claim 9 , wherein the at least one diode comprises a single crystalline silicon material.

12. The semiconductor device of claim 9 , wherein the adhesion material comprises amorphous silicon.

13. The semiconductor device of claim 9 , wherein the adhesion material comprises amorphous germanium.

14. A semiconductor device, comprising:
a first semiconductor substrate;
a second semiconductor substrate over and bonded to the first semiconductor substrate;
a conductive material comprised by the second substrate over an insulator material comprised by the first substrate;
a distinct amorphous adhesive material between and being in direct contact with each of the conductive material and the insulative material, the amorphous adhesive material comprising one or both of amorphous silicon and amorphous germanium, the amorphous adhesive material and the conductive material being commonly patterned;
at least one diode comprising a single crystalline silicon material over the conductive material, the at least one diode comprising:
a first doped region overlying the conductive material and a second doped region overlying the first doped region, wherein a conductivity type of the first doped region is opposite a conductivity type of the second doped region; and
a third doped region between the first and second doped regions, the third doped region being of conductivity type the same as one of the first and second doped regions but of lower dopant concentration than said one of the first and second doped regions; and

a memory cell over the second doped region.

Assignees

• Tang Sanh D
• Zhang Ming
• Micron Technology Inc

Inventors

• Tang Sanh D
• Zhang Ming

Classifications

• H10W10/011 Primary

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10 Primary

  Isolation regions comprising dielectric materials · CPC title

• H01L21/762 Primary

  Electricity · mapped topic

• H01L29/861

  Electricity · mapped topic

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title