Storage device and operating method thereof

Patent metadata

Field	Value
Publication number	US-9646706-B2
Application number	US-201615070122-A
Country	US
Kind code	B2
Filing date	Mar 15, 2016
Priority date	Mar 16, 2015
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

An operating method is for a storage device that includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory. The operating method may include the memory controller receiving a read request from an external device, the memory controller adjusting a read scheme according to target data indicated by the read request among data of one page of the nonvolatile memory, and the memory controller reading the target data from the nonvolatile memory according to the adjusted read scheme.

First claim

What is claimed is:

1. An operating method of a storage device including a nonvolatile memory and a memory controller configured to control the nonvolatile memory, the operating method comprising:
receiving, by the memory controller, a read request from an external device;
adjusting, by the memory controller, a read scheme of the nonvolatile memory; and
reading, by the memory controller, target data from the nonvolatile memory according to the adjusted read scheme,
wherein memory cells corresponding to a wordline and a selection line of the nonvolatile memory device constitute a page, and
adjusting the read scheme comprises adjusting levels of read voltages according to which a memory cell group among the memory cells of the one page is read.

2. The operating method of claim 1 , wherein the read request requests a read of partial data including the target data among data of one logical page among a plurality of logical pages corresponding to the one page.

3. The operating method of claim 1 , wherein the memory controller is configured to manage offsets of the read voltages corresponding to memory cell groups of the one page respectively.

4. The operating method of claim 1 , further comprising:
receiving, by the memory controller, a write request with respect to the one page;
setting, by the memory controller, information of state shaping of a plurality of codewords to be written in memory cell groups of the one page respectively, wherein the information of state shaping includes at least one of a respective number of bits of state shaping parities, ratios of desired states and type of state shaping algorithm;
performing, by the memory controller, a state shaping encoding with respect to the plurality of codewords using the state shaping parities having the respective number of bits differently set; and
programming, by the nonvolatile memory, the encoded codewords in the memory cell groups of the one page respectively.

5. The operating method of claim 4 , wherein adjusting the read scheme comprises adjusting, by the memory controller, a state shaping decoding scheme with respect to each codeword to be read according to the information of a state shaping.

6. The operating method of claim 4 , wherein the information of the state shaping is set according to a location of each memory cell group on the one page in which each codeword is programmed.

7. The operating method of claim 4 , wherein the information of the state shaping is set according to a bit error rate of each memory cell group of the one page in which each codeword is programmed.

8. The operating method of claim 1 , further comprising:
receiving, by the memory controller, at least first and second codewords;
interleaving, by the memory controller, the first and second codewords to generate interleaved codewords; and
programming, by the nonvolatile memory, the first and second interleaved codewords in the memory cell groups of the one page respectively,
wherein interleaving the first and second codewords comprises:
collecting a first portion of the first codeword and a first portion of the second codeword to generate the first interleaved codeword, and
collecting a second portion of the first codeword and a second portion of the second codeword to generate the second interleaved codeword.

9. The operating method of claim 8 , wherein adjusting the read scheme comprises adjusting the first and second interleaved codewords associated with at least one codeword as a read target according to the at least one codeword indicated by the read request.

10. The operating method of claim 8 , wherein generating the interleaved codewords comprises loading, by the memory controller, one codeword among the at least two codewords into the nonvolatile memory according to discontinuous addresses.

11. The operating method of claim 8 , wherein generating the first and second interleaved codewords comprises alternately loading, by the memory controller, the first portion of the codeword and a first portion of the second codeword into the nonvolatile memory according to continuous addresses.

12. The operating method of claim 8 , wherein generating the first and second interleaved codewords comprises generating the first interleaved codeword and second interleaved codeword by interleaving first codewords encoded by a first error correction block and second codewords encoded by a second error correction block,
wherein the first interleaved codeword and the second interleaved codeword are written to the one page of one of a first nonvolatile memory device and a second nonvolatile memory device through one of a first channel and a second channel corresponding to the first error correction block and the second error correction block respectively.

13. A storage device comprising:
a nonvolatile memory configured to store data in logical pages; and
a memory controller configured to control the nonvolatile memory;
wherein the memory controller is configured to adjust a read scheme of the nonvolatile memory,
memory cells corresponding to a wordline and a selection line of the nonvolatile memory device constitute one page, and
the memory controller adjusts a state shaping decoding scheme as the read scheme according to which memory cell group among the memory cells of the one page is read.

14. The storage device of claim 13 , wherein the nonvolatile memory comprises a three-dimensional cell array including a plurality of cell strings on a substrate, and wherein each cell string comprises a plurality of charge trap type memory cells and at least one charge trap type select transistor stacked in a direction perpendicular to the substrate.

15. The storage device of claim 13 , wherein the memory controller is configured to adjust the read scheme by levels of read voltages as the read scheme according to which memory cell group among the memory cells of the one page is read.

16. The storage device of claim 13 , wherein the memory controller is further configured to:
receive a write request with respect to the one page;
set a respective number of bits of state shaping parities of a plurality of codewords to be written in the memory cell groups of the one page respectively;
perform a state shaping encoding with respect to the plurality of codewords using the state shaping parities having the respective number of bits; and
program the encoded codewords in the memory cell groups of the one page respectively.

17. The storage device of claim 16 , wherein the memory controller is configured to adjust the state shaping decoding scheme with respect to each codeword according to a number of bits of a state shaping parity of each codeword.

18. The storage device of claim 13 , wherein the memory controller is further configured to:
receive at least two codewords;
interleave the received at least two codewords to generate interleaved codewords; and
program the interleaved codewords in the one page.

19. An operating method of a storage device including a nonvolatile memory and a memory controller configured to control the nonvolatile memory, the operating method comprising:
receiving, by the memory controller, a read request from an external device;
adjusting, by the memory controller, a read scheme of the nonvolatile memory; and
reading, by the memory controller, target data from the nonvolatile memory according to the adjusted read scheme,
wherein, the nonvolatile memory comprises a three-dimensional cell array including a plurality of cell strings on a substrate, each cell string comprisi

Assignees

• So Hyejeong
• Kong Junjin
• Seol Changkyu
• Son Hong Rak
• Choi Seonghyeog
• Samsung Electronics Co Ltd

Inventors

• So Hyejeong
• Kong Junjin
• Seol Changkyu
• Son Hong Rak
• Choi Seonghyeog

Classifications

• G11C29/021

  in voltage or current generators · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• H03M13/2707

  Simple row-column interleaver, i.e. pure block interleaving · CPC title

• H03M13/6508

  Flexibility, adaptability, parametrability and configurability of the implementation · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title