Semiconductor memory device tunnel insulating layers included in the plurality of memory cells having different thicknesses according to distances of the plurality of memory cells from the X-decoder

Patent metadata

Field	Value
Publication number	US-9646698-B2
Application number	US-201514813901-A
Country	US
Kind code	B2
Filing date	Jul 30, 2015
Priority date	Mar 25, 2015
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A semiconductor memory device includes a plurality of memory cells and an X-decoder. The plurality of memory cells are connected to a word line. The X-decoder is connected to the word line, and applies an operating voltage to the word line. In the semiconductor memory device, tunnel insulating layers included in the plurality of memory cells have different thicknesses according to distances of the plurality of memory cells from the X-decoder.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
an X-decoder suitable for applying a program voltage and a pass voltage to a plurality of word lines; and
a memory cell array including a plurality of cell strings, the memory cell array being connected to the plurality of word lines,
wherein channel plugs are formed to different widths according to positions at which the plurality of cell strings are arranged, and
wherein each of the plurality of cell strings includes:
insulative patterns and conductive patterns which are alternately stacked;
a channel layer that passes through the insulative patterns and the conductive patterns; and
a tunnel insulating layer that surrounds sidewalls of the channel layer.

2. The semiconductor memory device of claim 1 ,
wherein a width of a channel plug of a first cell string adjacent to the X-decoder is wider than a width of a channel plug of a second cell string which is located farther from the X-decoder than the channel plug of the first cell string.

3. The semiconductor memory device of claim 2 , wherein a length of the word line connecting the X-decoder to the first cell string is shorter than that of the word line connecting the X-decoder to the second cell string.

4. The semiconductor memory device of claim 1 , wherein a width of a channel plug of each of the plurality of cell strings becomes narrower as a distance of the cell strings from the X-decoder increases.

Assignees

• Sk Hynix Inc

Inventors

• Lee Yeonghun

Classifications

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic