10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof

Patent metadata

Field	Value
Publication number	US-9646694-B2
Application number	US-201514886663-A
Country	US
Kind code	B2
Filing date	Oct 19, 2015
Priority date	Oct 21, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

First claim

What is claimed is:

1. A memory comprising:
an array of non-volatile Static Random Access Memory (nvSRAM) cells, each nvSRAM cell comprising:
a volatile charge storage circuit;
a non-volatile charge storage circuit comprising exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT); and
a processing element to issue control signals to each of the nvSRAM cells to execute a STORE operation and a RECALL operation, wherein the processing element is configured to issue control signals for the STORE operation comprising control signals for normal programming in which the first transistor is ON and the second and third transistors are OFF, and a plurality of program pulses are applied to a gate node of the NVM element to mitigate an impact of Dynamic Write Inhibit (DWI).

2. The memory of claim 1 , wherein the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between VCCT and the first node of the NVM element.

3. The memory of claim 1 , wherein the third transistor is coupled between VCCT and a first node of the NVM element, and the first and second transistors are coupled to a second node of the NVM element.

4. The memory of claim 1 , wherein the volatile charge storage circuit comprises a cross-coupled static random access memory (SRAM) latch comprising a data node (dt) coupled to a bitline (BT) and to the first transistor of the NVM element, and a data complement node (dc) coupled to a bitline complement (BC) and to the second transistor of the NVM element.

5. The memory of claim 4 , wherein the NVM element comprises exactly one silicon-oxide-nitride-oxide-silicon (SONOS) transistor, or exactly one floating-gate MOS field-effect transistor (FGMOS).

6. The memory of claim 1 , wherein the processing element is configured to issue control signals so that data recalled out of the non-volatile charge storage circuit into the volatile charge storage circuit is non-inverted for every RECALL operation.

7. The memory of claim 1 , wherein the plurality of program pulses issued by the processing element each have a peak voltage of approximately 10V.

8. The memory of claim 1 , wherein each program pulse has a pulse width substantially equal to a time between program pulses.

9. The memory of claim 7 , wherein the processing element is configured to issue for the STORE operation control signals further comprising control signals for bulk programming to set the NVM element to a programmed state, and bulk erasing to set the NVM element to an erased state, prior to the normal programming.

10. A method of operating a non-volatile Static Random Access Memory (nvSRAM) cell including a volatile charge storage circuit and a non-volatile charge storage circuit, the method comprising:
turning ON a first transistor in the non-volatile charge storage circuit coupled between a non-volatile memory (NVM) element in the non-volatile charge storage circuit and a data node (dt) in the volatile charge storage circuit;
turning OFF second and third transistors in the non-volatile charge storage circuit, the second transistor coupled between the NVM element and a data complement node (dc) in the volatile charge storage circuit and the third transistor coupled between the NVM element and a positive voltage supply line (VCCT); and
applying a plurality program pulses to a gate node of the NVM element to STORE data from the volatile charge storage circuit to the non-volatile charge storage circuit, while mitigating Dynamic Write Inhibit (DWI) from the dt node,
wherein the non-volatile charge storage circuit comprises exactly one non-volatile memory (NVM) element.

11. The method of claim 10 , wherein the plurality of program pulses comprises a peak voltage of approximately 10V.

12. The method of claim 10 , wherein each program pulse has a pulse width substantially equal to a time between program pulses.

13. The method of claim 10 , further comprising initial steps of bulk programming to set the NVM element to a programmed state, and bulk erasing to set the NVM element to an erased state.

14. The method of claim 10 , wherein the NVM element comprises exactly one silicon-oxide-nitride-oxide-silicon (SONOS) transistor or exactly one polysilicon floating gate transistor.

15. A method of operating a non-volatile Static Random Access Memory (nvSRAM) cell comprising:
recalling data from a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element in the nvSRAM cell to a volatile charge storage circuit, wherein the data recalled is not inverted, further comprising:
limiting current through the nvSRAM cell by setting a control signal to a negative supply voltage (VSS) transistor to electrically disconnect a negative voltage supply line (VSSI) from a negative supply voltage, and clamping voltage between VSSI and a first positive voltage supply line (VCCI) coupled to the volatile charge storage circuit;
coupling a second positive voltage supply line (VCCT) to the non-volatile charge storage circuit to ground (VGND);
turning ON first and second transistors in the non-volatile charge storage circuit, the first transistor coupled between the NVM element and a data node (dt) in the volatile charge storage circuit, and the second transistor coupled between the NVM element and VCCT, so that data stored in the data node (dt) and data stored in a data complement node (dc) in the volatile charge storage circuit flips;
forcing a gate node of the NVM element to a voltage between an erased threshold voltage (Vte) and a programmed threshold voltage (Vtp);
turning ON a third transistor coupled between the NVM element and the dc node and turning OFF the first transistor; and
unclamping the voltage between VSSI and VCCI, and applying VSSI to the nvSRAM cell to latch non-inverted data from the non-volatile charge storage circuit to the volatile charge storage circuit.

16. The method of claim 15 , wherein the NVM element comprises exactly one silicon-oxide-nitride-oxide-silicon (SONOS) transistor or exactly one polysilicon floating gate transistor.

Assignees

• Cypress Semiconductor Corp

Inventors

• Tandingan Joseph S
• Ashokkumar Jayant
• Still David
• Siman Jesse J

Classifications

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C14/0063 Primary

  and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title