Butterfly channelizer

Patent metadata

Field	Value
Publication number	US-9645972-B2
Application number	US-201414320839-A
Country	US
Kind code	B2
Filing date	Jul 1, 2014
Priority date	Jun 16, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A butterfly channelizer includes at least two stages. Each stage includes at least one dual-channel module configured to convert an input time domain signal into a second time domain signal of lower bandwidth. At least one clock is configured to generate a clock signal that drives the at least two stages. A first stage has a first number of dual-channel modules and a second stage following the first stage has a second number of dual-channel modules greater than the first number.

First claim

What is claimed is:

1. A butterfly channelizer, comprising:
at least two stages, each stage including at least one dual-channel module configured to convert an input time domain signal into a second time domain signal of lower bandwidth at baseband; and
at least one clock configured to generate a clock signal that drives the at least two stages,
wherein a first stage has a first number of dual-channel modules and a second stage following the first stage has a second number of dual-channel modules greater than the first number.

2. The butterfly channelizer of claim 1 , wherein each stage among the at least two stages is selectively tapped to provide respective channel outputs.

3. The butterfly channelizer of claim 2 , wherein the second stage has a greater number of output channels than the first stage.

4. The butterfly channelizer of claim 3 , wherein the at least one clock comprises a single master clock configured to generate a master clock signal that is delivered to the first stage.

5. The butterfly channelizer of claim 4 , wherein the master clock signal is divided to generate a second clock signal that is delivered to the second stage.

6. The butterfly channelizer of claim 5 , wherein the output channels of the second stage have a narrower bandwidth than the output channels of the first stage.

7. The butterfly channelizer of claim 6 , wherein the at least two stages includes first stage including a first number of dual-channel modules to define the first stage among the at least two stages, a second number of dual-channel modules that is twice the number of the first number to define the second stage among the at least two stages, and a third number of dual-channel modules that is twice the second number to define a third stage among the at least two stages.

8. The butterfly channelizer of claim 7 , wherein the first stage has a plurality of first channel outputs having a first bandwidth, the second stage has a plurality of second channel outputs having a second bandwidth greater than the first bandwidth, and the third stage has a plurality of third channel outputs having a third bandwidth that is greater than the first and second bandwidths.

9. A method of channelizing an input time domain signal using a butterfly channelizer, the method comprising:
converting an input time domain signal into a plurality of corresponding second time domain signals of lower bandwidth at baseband using at least two stages;
generating at least one clock signal; and
in response to the clock signal, generating a first number of output channels from a first stage and generating a second number of output channels greater than the first number from a second stage following the first stage,
wherein converting the input time domain signal includes down-sampling, via analog sample-and-hold unit, the input time domain signal, filtering the input time domain signal, and increasing the signal to noise ratio of the down-sampled time domain signal to generate the second time domain signals and provide output channels of the at least two stages.

10. The method of claim 9 , further comprising applying a discrete Fourier transform algorithm on the down-sampled time domain signal.

11. The method of claim 9 , further comprising selectively tapping each stage among the at least two stages to provide respective channel outputs.

12. The method of claim 11 , wherein the second stage has a greater number of output channels than the first stage.

13. The method of claim 12 , further comprising generating a master clock signal that is delivered to the first stage.

14. The method of claim 13 , further comprising dividing the master clock signal to generate a second clock signal that is delivered to the second stage.

15. The method of claim 14 , wherein the output channels of the second stage have a narrower bandwidth than the output channels of the first stage.

16. The method of claim 15 , wherein the at least two stages includes a first number of dual-channel modules to define a first stage among the at least two stages, a second number of dual-channel modules that is twice the number of the first number to define a second stage among the at least two stages, and a third number of dual-channel modules that is twice the second number to define a third stage among the at least two stages.

17. The method of claim 16 , wherein the first stage has a plurality of first channel outputs having a first bandwidth, the second stage has a plurality of second channel outputs having a second bandwidth greater than the first bandwidth, and the third stage has a plurality of third channel outputs having a third bandwidth that is greater than the first and second bandwidths.

Assignees

• Raytheon Co

Inventors

• Marr Harry B
• Thompson Daniel

Classifications

• H03H17/0213

  Frequency domain filters using Fourier transforms · CPC title

• H03H17/0248

  Filters characterised by a particular frequency response or filtering method · CPC title

• G06F17/142 Primary

  Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm · CPC title

• H04B1/001 Primary

  Channel filtering, i.e. selecting a frequency channel within the SDR system (multiplexing of multicarrier modulation signals being represented by different frequencies H04L5/06; multiplexing of multicarrier modulation signals H04L5/023) · CPC title