Inter-processor communication techniques in a multiple-processor computing platform

Patent metadata

Field	Value
Publication number	US-9645866-B2
Application number	US-201113235236-A
Country	US
Kind code	B2
Filing date	Sep 16, 2011
Priority date	Sep 20, 2010
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

First claim

The invention claimed is:

1. A host device comprising:
one or more processors;
a command queue interface for execution by the one or more processors, wherein the command queue interface is configured to place a plurality of commands into a command queue in response to receiving one or more enqueue instructions from a process executing on the host device, the plurality of commands including a first command instructing the host device to transfer data between a first memory space associated with the host device and a second memory space associated with a graphics processing unit (GPU), the plurality of commands further including a second command instructing the host device to initiate execution of a task on the GPU;
a message passing interface for execution by the one or more processors, wherein the message passing interface is configured to pass one or more messages between the process executing on the host device and the task executing on the GPU while the task is executing on the GPU and in response to receiving one or more message passing instructions from the process executing on the host device; and
a memory buffer interface for execution by the one or more processors, wherein the memory buffer interface is configured to disable, via at least one register associated with a shared memory, caching services associated with the shared memory or a cache coherency mode associated with the shared memory to enable sharing of data between the process executing on the host device and the task executing on the GPU while the task is executing on the GPU, wherein the shared memory is accessible by the GPU and the host device.

2. The host device of claim 1 ,
wherein the one or more message passing instructions comprises a send instruction that instructs the message passing interface to send a message from the process executing on the host device to the task executing on the GPU, and
wherein the message passing interface is further configured to send, in response to receiving the send instruction, the message from the process executing on the host device to the task executing on the GPU while the task is executing on the GPU.

3. The host device of claim 1 ,
wherein the one or more message passing instructions comprises a register callback routine instruction that instructs the message passing interface to invoke a callback routine in response to receiving a signal from the GPU indicating that the task executing on the GPU has sent a message, and
wherein the message passing interface is further configured to initiate execution of the callback routine specified in the register callback routine instruction in response to receiving the signal from the GPU indicating that the task executing on the GPU has sent a message.

4. The host device of claim 1 ,
wherein the one or more message passing instructions comprises a polling instruction that instructs the message passing interface to poll the GPU for message status information indicative of whether the task executing on the GPU has sent a message, and
wherein the message passing interface is further configured to poll the GPU for the message status information in response to receiving the polling instruction, and when the message status information indicates that the task executing on the GPU has sent the message, obtain the message from the GPU.

5. The host device of claim 1 , wherein the task executing on the GPU includes an instruction that instructs the GPU to send a message from the task executing on the GPU to the process executing on the host device.

6. The host device of claim 1 , wherein the task executing on the GPU includes an instruction that instructs the GPU to determine whether a message sent to the task from the process executing on the host device is available, and to provide to the task the message when the message is available.

7. The host device of claim 1 , wherein the message passing interface is further configured to execute the one or more message passing instructions without placing any commands in the command queue.

8. A method comprising:
placing, with a command queue interface executing on one or more processors of a host device, a plurality of commands into a command queue in response to receiving one or more enqueue instructions from a process executing on the host device, the plurality of commands including a first command instructing the host device to transfer data between a first memory space associated with the host device and a second memory space associated with a graphics processing unit (GPU), the plurality of commands further including a second command instructing the host device to initiate execution of a task on the GPU;
passing, with a message passing interface executing on the one or more processors of the host device, one or more messages between the process executing on the host device and the task executing on the GPU while the task is executing on the GPU and in response to receiving one or more message passing instructions from the process executing on the host device; and
disabling, via a memory buffer interface executing by the host device and via at least one register associated with a shared memory, caching services associated with the shared memory or a cache coherency mode associated with the shared memory to enable sharing of data between the process executing on the host device and the task executing on the GPU while the task is executing on the GPU, wherein the shared memory is accessible by the GPU and the host device.

9. The method of claim 8 ,
wherein the one or more message passing instructions comprises a send instruction that instructs the message passing interface to send a message from the process executing on the host device to the task executing on the GPU, and
wherein the method further comprises sending, with the message passing interface, the message from the process executing on the host device to the task executing on the GPU while the task is executing on the GPU and in response to receiving the send instruction.

10. The method of claim 8 ,
wherein the one or more message passing instructions comprises a register callback routine instruction that instructs the message passing interface to invoke a callback routine in response to receiving a signal from the GPU indicating that the task executing on the GPU has sent a message, and
wherein the method further comprises initiating execution of the callback routine specified in the register callback routine instruction in response to receiving the signal from the GPU indicating that the task executing on the GPU has sent a message.

11. The method of claim 8 ,
wherein the one or more message passing instructions comprises a polling instruction that instructs the message passing interface to poll the GPU for message status information indicative of whether the task executing on the GPU has sent a message, and
wherein the method further comprises:
polling, with the message passing interface, the GPU for the message status information in response to receiving the polling instruction; and
when the message status information indicates that the task executing on the GPU has sent the message, obtaining the message from the GPU.

12. The method of claim 8 , wherein the task executing on the GPU includes an instruction that instructs the GPU to send a message from the task executing on the GPU to the process executing on the host device.

13. The method of claim 8 , wherein the task executing on the GPU includes an instruction that instructs the GPU to determine whether a message sent to the task from the process executing on the host device is available, and to provide to the task the message when th

Assignees

• Bourd Alexei V
• Sharp Colin Christopher
• Garcia Garcia David Rigel
• Zhang Chihong
• Qualcomm Inc

Inventors

• Bourd Alexei V
• Sharp Colin Christopher
• Garcia Garcia David Rigel
• Zhang Chihong

Classifications

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/54

  Interprogram communication · CPC title

• G06F9/544 Primary

  Buffers; Shared memory; Pipes · CPC title

• G06F9/546 Primary

  Message passing systems or structures, e.g. queues · CPC title

• G06T1/60

  Memory management · CPC title