Apparatus and method for early issue and recovery for a conditional load instruction having multiple outcomes
US-8977837-B2 · Mar 10, 2015 · US
Conditional store instructions in an out-of-order execution microprocessor
US9645822B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9645822-B2 |
| Application number | US-201214007097-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 6, 2012 |
| Priority date | Apr 7, 2011 |
| Publication date | May 9, 2017 |
| Grant date | May 9, 2017 |
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Abstract
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An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.
First claim
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We claim: 1. A microprocessor having an instruction set architecture that defines a conditional store instruction, the microprocessor comprising: a store queue; a register file; an instruction translator, that translates the conditional store instruction into at least two microinstructions, wherein the conditional store instruction specifies a data register, a base register, and an offset register of the register file, wherein the conditional store instruction instructs the mi…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F9/3017Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9645822B2 cover?
- An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first resu…
- Who is the assignee on this patent?
- Henry G Glenn, Parks Terry, Hooker Rodney E, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G06F9/3017. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue May 09 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).