Framework for balancing robustness and latency during collection of statistics from soft reads

US9645763B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9645763-B2
Application numberUS-201414181893-A
CountryUS
Kind codeB2
Filing dateFeb 17, 2014
Priority dateJan 13, 2014
Publication dateMay 9, 2017
Grant dateMay 9, 2017

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Abstract

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An apparatus includes a plurality of memory devices and a controller. The controller is coupled to the plurality of memory devices and configured to store data in the plurality of memory devices using units of super-blocks. Each super-block comprises a block from each of the plurality of memory devices and the controller balances time efficiency and robustness during collection of statistics from soft reads of each super-block.

First claim

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The invention claimed is: 1. An apparatus comprising: a memory comprising a plurality of memory devices; and a controller coupled to the memory and configured to process a plurality of read/write operations to/from the memory, store data in the plurality of memory devices using units of super-blocks, and generate a number of unique weight statistics in a single read operation by reading a number of dies within a super-block with dissimilar read reference voltages, wherein each super-block comprises a block from a die of each of the plurality of memory devices, and the number of unique weight statistics are represented by 3-tuple vectors of weights. 2. The apparatus according to claim 1 , wherein the controller is further configured to balance time efficiency and robustness during collection of statistics from soft reads of each super-block by setting a number of parameters of an adaptive tracking routine. 3. The apparatus according to claim 2 , wherein the parameters comprise a first parameter defining a number of dies in a group and a second parameter defining a number of groups. 4. The apparatus according to claim 3 , wherein the adaptive tracking routine is configured to average a number of page weights collected from within each group. 5. The apparatus according to claim 1 , wherein the controller is further configured to perform one or more of: averaging page weights on a component weight basis; and choosing pages across the dies of each super-block such that the pages are distributed to average out page-to-page variation. 6. The apparatus according to claim 1 , wherein the controller is further configured to split the number of dies in each super-block into two sets and collect page weights for upper pages from one of the two sets and page weights for lower pages from the other of the two sets. 7. The apparatus according to claim 6 , wherein: across all lower page reads, MSB related voltages are set to default or previously tracked read reference voltages; across all upper page reads, LSB related voltages are set to default or previously tracked read reference voltages; and averaging and interleaving are applied within each set. 8. The apparatus according to claim 1 , wherein the memory and the controller are part of a solid state drive (SSD). 9. A method of collecting statistics from soft reads of a flash memory comprising: storing data in a plurality of flash memory devices using units of super-blocks, wherein each super-block comprises a block from a die of each of the plurality of flash memory devices; and generating a number of unique weight statistics in a single read operation by reading a number of the dies within a super-block with dissimilar read reference voltages, wherein the number of unique weight statistics are represented by 3-tuple vectors of weights. 10. The method according to claim 9 , further comprising: splitting the number of dies in each super-block into two sets to collect page weights for upper and lower pages. 11. The method according to claim 10 , wherein: across all lower page reads, MSB related voltages are set to default or previously tracked read reference voltages; across all upper page reads, LSB related voltages are set to default or previously tracked read reference voltages; and averaging and interleaving are applied within each set. 12. The method according to claim 9 , further comprising: choosing pages across the dies of each super-block such that the pages are distributed to average out page-to-page variation. 13. The method according to claim 9 , further comprising: balancing time efficiency and robustness during collection of statistics from soft reads of each super-block by setting a number of parameters of an adaptive tracking routine. 14. The method according to claim 13 , wherein the parameters comprise a first parameter defining a number of dies in a group and a second parameter defining a number of groups in each super-block. 15. The method according to claim 14 , wherein the adaptive tracking routine is configured to average a number of page weights collected from within a group. 16. An apparatus comprising: an interface configured to process a plurality of read/write operations to/from a memory comprising a plurality of memory devices; and a control circuit configured to store data in the plurality of memory devices using units of super-blocks, balance time efficiency and robustness during collection of statistics from soft reads of each super-block, and generate a number of unique weight statistics in a single read operation by reading a number of dies within a super-block with dissimilar read reference voltages, wherein each super-block comprises a block from a die of each of the plurality of memory devices, and the number of unique weight statistics are represented by 3-tuple vectors of weights. 17. The apparatus according to claim 16 , wherein the control circuit is further configured to split the number of dies in each super-block into two sets and collect page weights for upper pages from one of the two sets and page weights for lower pages from the other of the two sets. 18. The apparatus according to claim 16 , wherein the interface and the control circuit are part of a solid state drive (SSD) controller.

Assignees

Inventors

Classifications

  • G06F3/0653Primary

    Monitoring storage devices or systems · CPC title

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • Non-volatile semiconductor memory arrays · CPC title

  • G06F3/0611Primary

    in relation to response time · CPC title

  • Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

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What does patent US9645763B2 cover?
An apparatus includes a plurality of memory devices and a controller. The controller is coupled to the plurality of memory devices and configured to store data in the plurality of memory devices using units of super-blocks. Each super-block comprises a block from each of the plurality of memory devices and the controller balances time efficiency and robustness during collection of statistics fr…
Who is the assignee on this patent?
Seagate Technology Llc
What technology area does this patent fall under?
Primary CPC classification G06F3/0653. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 09 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).