Array substrate, display device, and method for manufacturing the array substrate

Patent metadata

Field	Value
Publication number	US-9645457-B2
Application number	US-94397607-A
Country	US
Kind code	B2
Filing date	Nov 21, 2007
Priority date	Nov 22, 2006
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

An array substrate has regions in which an intermediate resist film thickness is formed and processed by an intermediate exposure amount which does not completely expose a resist, respectively on a drain electrode, source terminal, and a common connection wiring which are made of a second conductive film. Thin film patterns or a common wiring made of a first conductive film is formed in substantially entire regions on the bottom layers of the regions so that the heights from a substrate are substantially the same.

First claim

What is claimed is:

1. An array substrate comprising:
a substrate;
a first conductive film;
an insulation film formed on the first conductive film; and
a second conductive film formed on the insulation film, the second conductive film including a plurality of regions including upper thin film patterns formed by processing a resist to form an intermediate resist film thickness by an intermediate exposure amount which does not completely expose the resist,
wherein the first conductive film includes a common wiring and a thin film pattern formed in an entire area below each of the plurality of regions including the upper thin film patterns of the second conductive film, and heights of the thin film patterns of the first conductive film from the substrate are the same, and
wherein the thin film pattern is electrically-isolated from other wirings.

2. The array substrate according to claim 1 , further comprising:
a semiconductor film formed on the insulation film, including a lower thin film pattern formed in an entire area below at least one of the plurality of regions including the upper thin film patterns, and heights of the lower thin film patterns from the substrate are the same.

3. The array substrate according to claim 1 ,
wherein the second conductive film includes a multilayer film having at least two layers, and at least an upper layer film of the second conductive film is removed in at least one of the plurality of regions.

4. The array substrate according to claim 1 , wherein the upper thin film patterns in the plurality of regions include at least two of a drain electrode thin film pattern, a source terminal thin film pattern, and a common wiring conversion part thin film pattern.

5. The array substrate according to claim 1 , wherein the upper thin film patterns in the plurality of regions include at least two of a drain electrode thin film pattern, a source terminal thin film pattern, and a common wiring conversion part thin film pattern.

6. The array substrate according to claim 1 , wherein the plurality of regions include at least three laminated structures.

7. The array substrate according to claim 1 , wherein the plurality of regions include at least three laminated structures.

8. The array substrate according to claim 1 , wherein a pixel in a display part, a source terminal, and a common wiring conversion portion are formed in the plurality of regions, and
wherein the thin film pattern is formed in an entire area below at least the pixel in the display part and the source terminal.

9. The array substrate according to claim 1 , wherein the thin film pattern is formed only in an entire area below each of the plurality of regions including the upper thin film patterns of the second conductive film, and
wherein, in the plurality of regions, heights of the upper thin film pattern in the second conductive film from the substrate are the same as each other.

10. The array substrate according to claim 1 , wherein the upper thin film patterns of the second conductive film include at least one of a source terminal film, a source electrode and a drain electrode of an electrostatic protection circuit.

11. The array substrate according to claim 1 , further comprising:
an interlayer insulating film, which covers the upper thin film patterns of the second conductive film; and
a pixel electrode, which is in contact with the upper thin film pattern via a contact hole opened in the interlayer insulating film,
wherein the contact hole is overlapped with the thin film pattern, as viewed from above.

12. The array substrate according to claim 1 , wherein the thin film pattern is electrically-isolated from at least the common wiring and a gate wiring.

13. The array substrate according to claim 1 , wherein the thin film pattern is electrically-isolated from all other wirings so that there is not any voltage applied to the thin film pattern.

14. A display device using an array substrate, the array substrate comprising:
a substrate;
a first conductive film;
an insulation film formed on the first conductive film; and
a second conductive film formed on the insulation film, the second conductive film including a plurality of regions including upper thin film patterns formed by processing a resist to form an intermediate resist film thickness by an intermediate exposure amount which does not completely expose the resist,
wherein the first conductive film includes a common wiring and a thin film pattern formed in an entire area below each of the plurality of regions including the upper thin film patterns of the second conductive film, and heights of the thin film patterns of the first conductive film from the substrate are the same, and
wherein the thin film pattern is electrically-isolated from other wirings.

15. The display device according to claim 14 , wherein the upper thin film patterns in the plurality of regions include at least two of a drain electrode thin film pattern, a source terminal thin film pattern, and a common wiring conversion part thin film pattern.

16. A method for manufacturing an array substrate, comprising:
forming an insulation film on a first conductive film;
forming a second conductive film on the insulation film, the second conductive film including a plurality of regions including upper thin film patterns, and the forming the second conductive film including
forming a resist, and
processing the resist to form an intermediate resist film thickness by an intermediate exposure amount which does not completely expose the resist; and

forming a common wiring and thin film patterns of the first conductive film in an entire area below each of the plurality of regions including the upper thin film patterns of the second conductive film such that heights of the thin film patterns of the first conductive film from the substrate are the same,
wherein the thin film patterns are electrically-isolated from other wirings.

17. The method according to claim 16 , wherein forming the second conductive film includes:
forming, in the second conductive film, a multilayer film having at least two layers; and
removing at least an upper layer film of the second conductive film in each of the plurality of regions.

Assignees

• Masutani Yuichi
• Noumi Shigeaki
• Shimamura Takeshi
• Aoki Masaru
• Mitsubishi Electric Corp

Inventors

• Masutani Yuichi
• Noumi Shigeaki
• Shimamura Takeshi
• Aoki Masaru

Classifications

• Y10T428/24802

  Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] · CPC title

• G02F1/1362 Primary

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title

• G02F2201/48

  Flattening arrangements · CPC title