Transparent display device and manufacturing method thereof

US9645434B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9645434-B2
Application numberUS-201414292521-A
CountryUS
Kind codeB2
Filing dateMay 30, 2014
Priority dateOct 8, 2013
Publication dateMay 9, 2017
Grant dateMay 9, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Discussed are a transparent display device and a manufacturing method thereof, which may reduce diffraction grating. The transparent display device includes gate lines and data lines formed on a substrate and crossing each other with a gate insulator film interposed therebetween to define pixel areas, common lines formed on the substrate and being parallel to the gate lines, thin film transistors formed in the respective pixel areas, pixel electrodes connected to the thin film transistors, and common electrodes connected to the common lines and alternating with the pixel electrodes. In the transparent display device, blocks between the pixel electrodes and the common electrodes are reduced or increased in width by an equal difference with increasing distance from both edges of each pixel area proximate to the data lines or by an equal difference with decreasing distance to the center of the pixel area.

First claim

Opening claim text (preview).

What is claimed is: 1. A transparent display device comprising: gate lines and data lines formed on a substrate, the gate lines and the data lines crossing each other with a gate insulator film interposed therebetween to define pixel areas; common lines formed on the substrate, the common lines being parallel to the gate lines; thin film transistors formed in the respective pixel areas; pixel electrodes connected to the thin film transistors; and common electrodes connected to the common lines, the common electrodes alternating with the pixel electrodes, wherein a width of each block disposed between each of the pixel electrodes and the common electrodes is sequentially varied by an equal amount with an increasing distance from both edges of each pixel area to a center of the pixel area, and wherein the equal amount is within a range of 0.5 μm to 1 μm. 2. The device according to claim 1 , wherein the blocks between the pixel electrodes and the common electrodes are symmetrical on the basis of the center between the two data lines proximate to both edges of the pixel area. 3. The device according to claim 1 , wherein the width of each block disposed between each of the pixel electrodes and the common electrodes is sequentially reduced or increased by an equal amount with an increasing distance from both edges of each pixel area to a center of the pixel area. 4. A transparent display device comprising: gate lines and common lines on a substrate, the gate lines and the common lines being parallel to each other; a gate insulator film on the substrate including the gate lines and the common lines; data lines on the gate insulator film, the data lines crossing the gate lines to define pixel areas; thin film transistors in the respective pixel areas; a protective film on the substrate to cover the data lines and the thin film transistors; pixel electrodes on the protective film within each pixel area, the pixel electrodes connected to the thin film transistors; and common electrodes on the protective film within each pixel area, the common electrodes connected to the common lines, the common electrodes alternating with the pixel electrodes, wherein a width of each block disposed between each of the pixel electrodes and the common electrodes is sequentially varied by an equal amount with an increasing distance from both edges of each pixel area to a center of the pixel area, and wherein the equal amount is within a range of 0.5 μm to 1 μm. 5. The device according to claim 4 , further comprising: drain contact holes in the protective film on drain electrodes of the thin film transistors; and common contact holes in the protective film and the gate insulator film on the common lines, wherein the pixel electrodes are connected to the drain electrodes of the thin film transistors through the drain contact holes, and the common electrodes are connected to the common lines through the common contact holes. 6. The device according to claim 4 , wherein the blocks between the pixel electrodes and the common electrodes are symmetrical on the basis of the center between the two data lines proximate to both edges of the pixel area. 7. The device according to claim 4 , wherein each of the pixel electrodes includes a pixel horizontal portion which constitutes a storage capacitor in a region overlapping the common line, and a plurality of pixel vertical portions protruding from the pixel horizontal portion, and wherein each of the common electrode includes a plurality of common vertical portions alternating with the pixel vertical portions, and a common horizontal portion connecting the plurality of common vertical portions to one another. 8. The device according to claim 7 , wherein blocks between the pixel vertical portions and the common vertical portions are symmetrical on the basis of the center between the two data lines proximate to both edges of the pixel area. 9. The device according to claim 4 , wherein the width of each block disposed between each of the pixel electrodes and the common electrodes is sequentially reduced or increased by an equal amount with an increasing distance from both edges of each pixel area to a center of the pixel area. 10. A manufacturing method of a transparent display device, comprising: forming gate lines and common lines on a substrate, the gate lines and the common lines being parallel to each other; forming a gate insulator film on the substrate to cover the gate lines and the common lines; forming data lines on the gate insulator film, the data lines crossing the gate lines to define pixel areas; forming thin film transistors in the respective pixel areas; forming pixel electrodes connected to the thin film transistors; and forming common electrodes connected to the common lines, the common electrodes alternating with the pixel electrodes, wherein a width of each block disposed between each of the pixel electrodes and the common electrodes is sequentially varied by an equal amount with an increasing distance from both edges of each pixel area to a center of the pixel area, and wherein the equal amount is within a range of 0.5 μm to 1 μm. 11. The method according to claim 10 , wherein the blocks between the pixel electrodes and the common electrodes are symmetrical on the basis of the center between the two data lines proximate to both edges of the pixel area.

Assignees

Inventors

Classifications

  • pixel · CPC title

  • Antiglare, refractive index matching layers · CPC title

  • Constructional arrangements; {Manufacturing methods}(G02F1/135, G02F1/136 take precedence) · CPC title

  • for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

  • Wiring, e.g. gate line, drain line · CPC title

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What does patent US9645434B2 cover?
Discussed are a transparent display device and a manufacturing method thereof, which may reduce diffraction grating. The transparent display device includes gate lines and data lines formed on a substrate and crossing each other with a gate insulator film interposed therebetween to define pixel areas, common lines formed on the substrate and being parallel to the gate lines, thin film transisto…
Who is the assignee on this patent?
Lg Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/133504. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 09 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).