Capacitance reduction for pillar structured devices

Patent metadata

Field	Value
Publication number	US-9645262-B2
Application number	US-201414555463-A
Country	US
Kind code	B2
Filing date	Nov 26, 2014
Priority date	Nov 26, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

In one embodiment, an apparatus includes: a first layer including a n+ dopant or p+ dopant; an intrinsic layer formed above the first layer, the intrinsic layer including a planar portion and pillars extending above the planar portion, cavity regions being defined between the pillars; and a second layer deposited on a periphery of the pillars thereby forming coated pillars, the second layer being substantially absent on the planar portion of the intrinsic layer between the coated pillars. The second layer includes an n+ dopant when the first layer includes a p+ dopant. The second layer includes a p+ dopant when the first layer includes an n+ dopant. The apparatus includes a neutron sensitive material deposited between the coated pillars and above the planar portion of the intrinsic layer. In additional embodiments, an upper portion of each of the pillars includes a same type of dopant as the second layer.

First claim

What is claimed is:

1. An apparatus, comprising:
a first layer including an n+ dopant or a p+ dopant;
an intrinsic layer grown or deposited above the first layer, the intrinsic layer including a planar portion and pillars extending above the planar portion, wherein cavity regions are defined between the pillars;
a second layer deposited on a periphery of the pillars thereby forming coated pillars, wherein the second layer is substantially absent on the planar portion of the intrinsic layer between the coated pillars, wherein the second layer includes a n+ dopant when the first layer includes a p+ dopant, wherein the second layer includes a p+ dopant when the first layer includes a n+ dopant; and
a neutron sensitive material deposited between the coated pillars and above the planar portion of the intrinsic layer.

2. The apparatus as recited in claim 1 , wherein the apparatus has a capacitance of less than about 0.2 nF/cm 2 .

3. The apparatus as recited in claim 1 , wherein the pillars have an average aspect ratio of about 25:1.

4. The apparatus as recited in claim 1 , wherein each pillar has a width in a range from about 0.1 μm to about 10 μm.

5. The apparatus as recited in claim 4 , wherein a thickness of the second layer is greater than or equal to about 100 Å.

6. The apparatus as recited in claim 5 , wherein the thickness of the second layer is less than or equal to about 25% of an average width of the pillars.

7. The apparatus as recited in claim 1 , wherein at least one of the first layer, the intrinsic layer and the second layer comprise silicon.

8. The apparatus as recited in claim 1 , wherein at least one of the first layer, the intrinsic layer and the second layer comprise an III-V or II-VI semiconductor material.

9. The apparatus as recited in claim 8 , wherein the semiconductor material is selected from a group consisting of Si, SiC, GaAs, AlGaAs, GaN, AlGaN, InP, InGaAsP, and GaP.

10. The apparatus as recited in claim 1 , wherein the intrinsic layer has an n-type doping concentration in a range from about 1>10 11 dopants/cm −3 to about 1×10 16 dopants/cm −3 .

11. The apparatus as recited in claim 10 , wherein the second layer includes a p+ dopant with a p+ doping concentration that is greater than or equal to about 100 times that of the n-type doping concentration in the intrinsic layer.

12. The apparatus as recited in claim 1 , further comprising a passivation layer deposited on the planar portion of the intrinsic layer between the coated pillars.

13. The apparatus as recited in claim 12 , wherein the passivation layer comprises a dielectric material.

14. The apparatus as recited in claim 12 , wherein the passivation layer comprises an oxide.

15. The apparatus as recited in claim 1 , wherein each of the pillars has an upper portion positioned farthest from the planar portion of the intrinsic layer, wherein the upper portion of each of the pillars includes a same type of dopant as the second layer.

16. A method of forming the apparatus of claim 1 , comprising:
providing a substrate comprising the first layer and the intrinsic layer;
removing portions of the intrinsic layer to form the pillars and the cavity regions therebetween;
depositing the second layer on the periphery of the pillars and the planar portion of the intrinsic layer between the coated pillars;
protecting the second layer with a first etch mask;
protecting each top of the coated pillars having the first etch mask thereon with a second etch mask;
removing the second layer and first etch mask from the planar portion of the intrinsic layer between the coated pillars;
removing the second etch mask from each top of the coated pillars;
removing the first etch mask from the periphery of the coated pillars; and
depositing the neutron sensitive material between the coated pillars and above the planar portion of the intrinsic layer.

17. The method as recited in claim 16 , wherein depositing the second layer comprises a technique selected from a group consisting of: solid source diffusion doping, immersion ion implantation, gaseous diffusion doping, and spin coating.

18. The method as recited in claim 16 , wherein removing the second layer and the first etch mask from the planar portion of the intrinsic layer between the coated pillars comprises a highly directional plasma etching process.

19. The method as recited in claim 16 , further comprising depositing a passivation layer on the planar portion of the intrinsic layer between the coated pillars prior to depositing the neutron sensitive material.

20. An apparatus, comprising:
a first layer including an n+ dopant or a p+ dopant;
an intrinsic layer grown or deposited above the first layer, the intrinsic layer including a planar portion and pillars extending above the planar portion, wherein cavity regions are defined between the pillars;
a second layer deposited on a periphery of the pillars thereby forming coated pillars, wherein the second layer is substantially absent on the planar portion of the intrinsic layer between the coated pillars, wherein the second layer includes a p+ dopant when the first layer includes a n+ dopant, wherein the second layer includes a n+ dopant when the first layer includes a p+ dopant;
a passivation layer deposited on the planar portion of the intrinsic layer between the coated pillars;
a neutron sensitive material deposited between the coated pillars and above the passivation layer;
a first electrode in contact with the coated pillars; and
a second electrode in contact with the first layer,
wherein the passivation layer includes at least one of a dielectric material and a polymeric material,
wherein at least one of the first layer, the intrinsic layer and the second layer include an III-V or II-VI semiconductor material.

Assignees

• L Livermore Nat Security Llc

Inventors

• Shao Qinghui
• Conway Adam
• Nikolic Rebecca J
• Voss Lars
• Bhat Ishwara B
• Harrison Sara E

Classifications

• H01L31/117

  Electricity · mapped topic

• G01T3/08 Primary

  with semiconductor detectors · CPC title

• H10F30/292

  Bulk-effect radiation detectors, e.g. Ge-Li compensated PIN gamma-ray detectors · CPC title

• H10F30/29

  the devices being sensitive to radiation having very short wavelengths, e.g. X-rays, gamma-rays or corpuscular radiation · CPC title