System for testing integrated circuit

Patent metadata

Field	Value
Publication number	US-9645195-B2
Application number	US-201414288358-A
Country	US
Kind code	B2
Filing date	May 27, 2014
Priority date	May 27, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.

First claim

The invention claimed is:

1. An integrated circuit connectable to an automated test equipment (ATE) by way of at least one pogo pin for testing the integrated circuit, the integrated circuit comprising:
a voltage controlled oscillator (VCO) having an input terminal connected to the at least one pogo pin, for receiving first, second, third, and fourth reference voltage signals during first, second, third, and fourth time intervals, respectively, and an output terminal for outputting first, second, third, and fourth reference frequency signals corresponding to the first, second, third, and fourth reference voltage signals during the first, second, third, and fourth time intervals, respectively;
an analog-to-digital converter (ADC) having a first input terminal for receiving an analog signal, a second input terminal connected to the at least one pogo pin for receiving the third reference voltage signal during the third time interval, a third input terminal connected to the at least one pogo pin for receiving the fourth reference voltage signal during the fourth time interval, and an output terminal for outputting a digital signal based on the analog signal and the third and fourth reference voltage signals; and
a compensation circuit connected to the output terminals of the VCO and the ADC for generating a compensated digital signal based on the digital signal and the first, second, third, and fourth reference frequency signals.

2. The integrated circuit of claim 1 , wherein the compensation circuit includes:
a compensation factor calculation circuit connected to the output terminal of the VCO for receiving the first, second, third, and fourth reference frequency signals, and generating a compensation factor signal based on the first, second, third, and fourth reference frequency signals; and
a multiplier circuit connected to the compensation factor calculation circuit for receiving the compensation factor signal and to the output terminal of the ADC for receiving the digital signal, for generating the compensated digital signal based on the compensation factor signal and the digital signal.

3. The integrated circuit of claim 2 , wherein the multiplier circuit multiplies the compensation factor signal and the digital signal to generate the compensated digital signal.

4. The integrated circuit of claim 2 , wherein the compensation factor signal corresponds to a ratio of a difference between voltage levels of the third and fourth reference voltage signals to a difference between voltage levels of the first and second reference voltage signals.

5. The integrated circuit of claim 4 , wherein the digital signal is proportional to a ratio of a voltage level of the analog signal to the difference between the voltage levels of the third and fourth reference voltage signals, wherein the ratio of the voltage level of the analog signal to the difference between the voltage levels of the third and fourth reference voltage signals is multiplied by an Nth power of 2, where N is an integer.

6. The integrated circuit of claim 5 , wherein the compensated digital signal is proportional to a ratio of the voltage level of the analog signal to the difference between the voltage levels of the first and second reference voltage signals, wherein the ratio of the voltage level of the analog signal to the difference between the voltage levels of the first and second reference voltage signals is multiplied by the Nth power of 2.

7. The integrated circuit of claim 1 , wherein the first and second reference voltage signals are ideal high and low reference voltage signals, respectively, and the third and fourth reference voltage signals are erroneous high and low reference voltage signals, respectively.

8. An integrated circuit connectable to an automated test equipment (ATE) by way of at least one pogo pin for testing the integrated circuit, the integrated circuit comprising:
a voltage controlled oscillator (VCO) having an input terminal connected to the at least one pogo pin, for receiving first, second, third, and fourth reference voltage signals during first, second, third, and fourth time intervals, respectively and an output terminal for outputting first, second, third, and fourth reference frequency signals corresponding to the first, second, third, and fourth reference voltage signals during the first, second, third, and fourth time intervals, respectively;
an analog-to-digital converter (ADC) having a first input terminal for receiving an analog signal, a second input terminal connected to the at least one pogo pin for receiving the third reference voltage signal during the third time interval, a third input terminal connected to the at least one pogo pin for receiving the fourth reference voltage signal during the fourth time interval, and an output terminal for outputting a digital signal based on the analog signal and the third and fourth reference voltage signals; and
a compensation circuit connected to the output terminals of the VCO and the ADC for generating a compensated digital signal based on the digital signal and the first, second, third, and fourth reference frequency signals, wherein the compensation circuit includes:
a compensation factor calculation circuit for receiving the first, second, third, and fourth reference frequency signals during the first, second, third, and fourth time intervals, respectively, and generating a compensation factor signal; and
a multiplier circuit connected to the compensation factor calculation circuit for receiving the compensation factor signal and to the output terminal of the ADC for receiving the digital signal, for generating a compensated digital signal based on the compensation factor and the digital signals.

9. The integrated circuit of claim 8 , wherein the multiplier circuit multiplies the compensation factor and digital signals to generate the compensated digital signal.

10. The integrated circuit of claim 8 , wherein the compensation factor signal corresponds to a ratio of a difference between voltage levels of the third and fourth reference voltage signals to a difference between voltage levels of the first and second reference voltage signals.

11. The integrated circuit of claim 10 , wherein the digital signal is proportional to a ratio of a voltage level of the analog signal to the difference between the voltage levels of the third and fourth reference voltage signals, wherein the ratio of the voltage level of the analog signal to the difference between the voltage levels of the third and fourth reference voltage signals is multiplied by an Nth power of 2, where N is an integer.

12. The integrated circuit of claim 11 , wherein the compensated digital signal is proportional to a ratio of the voltage level of the analog signal to the difference between the voltage levels of the first and second reference voltage signals, wherein the ratio of the voltage level of the analog signal to the difference between the voltage levels of the first and second reference voltage signals is multiplied by the Nth power of 2.

13. The integrated circuit of claim 8 , wherein the first and second reference voltage signals are ideal high and low reference voltage signals, respectively, and the third and fourth reference voltage signals are erroneous high and low reference voltage signals, respectively.

14. A method of compensating a digital signal output by an analog-to-digital converter (ADC) of an integrated circuit that is connectable to an automated test equipment (ATE) by way of at least one pogo pin, wherein a voltage drop across the pogo pin causes an error in the digital signal, the method comprising:
generating first, se

Assignees

• Abhishek Kumar
• Kamal Kushal
• Sapra Vandana
• Freescale Semiconductor Inc

Inventors

• Abhishek Kumar
• Kamal Kushal
• Sapra Vandana

Classifications

• G01R31/2856 Primary

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/40

  recirculation type · CPC title

• H03M1/42

  Sequential comparisons in series-connected stages with no change in value of analogue signal · CPC title

• H03M1/466

  using switched capacitors · CPC title