Method for positioning semiconductor devices and corresponding positioning apparatus
US-2024329125-A1 · Oct 3, 2024 · US
Test carrier
US9645173B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9645173-B2 |
| Application number | US-201314405054-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 27, 2013 |
| Priority date | Jun 5, 2012 |
| Publication date | May 9, 2017 |
| Grant date | May 9, 2017 |
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- Title
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- Abstract
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- First independent claim
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Abstract
Official abstract text for this publication.
A test carrier includes a base member and a cover member. The base member includes a multi-layer board including a wiring line that is electrically connected to a die and a base film that supports the multi-layer board. The cover member includes a frame-shaped cover frame having an opening formed therein. The size of the multi-layer board is larger than the size of the die and is smaller than the size of the opening in a direction along a surface that is opposite to the die.
First claim
Opening claim text (preview).
The invention claimed is: 1. A test carrier comprising: a base that holds an electronic device to be tested; and a cover that overlaps the base so as to cover the electronic device to be tested, wherein the base includes: a multi-layer board including a wiring line that is electrically connected to the electronic device to be tested; and a supporting board that supports the multi-layer board, the cover includes a frame having an opening formed therein, and a size of the multi-layer board is larger than a size of the electronic device to be tested and is smaller than a size of the opening in a direction along a opposite surface which is opposite to the electronic device to be tested. 2. The test carrier according to claim 1 , wherein the base includes an external terminal, and the wiring line of the multi-layer board is connected to the external terminal through a wiring line of the supporting board. 3. The test carrier according to claim 2 , wherein the wiring line of the supporting board is formed outside the wiring line of the multi-layer board in the direction along the opposite surface.
Assignees
Inventors
Classifications
- G01R1/0483Primary
Sockets for unleaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips · CPC title
- G01R1/0441Primary
Details · CPC title
Testing of individual semiconductor devices (testing of photovoltaic devices H02S50/10; testing or measuring during manufacture or treatment {H10P74/00}) · CPC title
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Frequently asked questions
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- What does patent US9645173B2 cover?
- A test carrier includes a base member and a cover member. The base member includes a multi-layer board including a wiring line that is electrically connected to a die and a base film that supports the multi-layer board. The cover member includes a frame-shaped cover frame having an opening formed therein. The size of the multi-layer board is larger than the size of the die and is smaller than t…
- Who is the assignee on this patent?
- Advantest Corp
- What technology area does this patent fall under?
- Primary CPC classification G01R1/0483. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue May 09 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).