Integrated microfluidics system

US9643181B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9643181-B1
Application numberUS-201615017998-A
CountryUS
Kind codeB1
Filing dateFeb 8, 2016
Priority dateFeb 8, 2016
Publication dateMay 9, 2017
Grant dateMay 9, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A microfluidic system-on-a-chip includes signal processing, light generation and detection, and fluid handling functions formed on a single substrate. The disclosed integrated system has a smaller footprint than device structures where individual components are manufactured separately and then assembled. Moreover, the integrated system obviates alignment challenges associated with conventionally packaged architecture.

First claim

Opening claim text (preview).

What is claimed as new is: 1. A microfluidic device comprising: an integrated circuitry located in a first region of a semiconductor substrate; a trench located in a second region of the semiconductor substrate and filled with an epitaxial layer; a light source located in a first region of the epitaxial layer a light detector located in a second region of the epitaxial layer; and a microfluidic flow channel within a dielectric layer disposed over the semiconductor substrate and the epitaxial layer. 2. The microfluidic device of claim 1 , wherein the integrated circuitry comprises transistors, memory cells and electrical contacts. 3. The microfluidic device of claim 1 , wherein a top surface of each of the light source and the light detector is coplanar with a top surface of the semiconductor substrate. 4. The microfluidic device of claim 1 , wherein the microfluidic flow channel is disposed over the light source and the light detector. 5. The microfluidic device of claim 1 , further comprising an interconnect layer between the dielectric layer and the semiconductor substrate. 6. The microfluidic device of claim 1 , wherein the epitaxial layer comprises gallium nitride. 7. The microfluidic device of claim 1 , further comprising a light blocking layer within the epitaxial layer between the light source and the light detector. 8. The microfluidic device of claim 1 , wherein the semiconductor substrate comprises silicon and the dielectric layer comprises silicon dioxide. 9. A method of forming a microfluidic device, comprising: forming an integrated circuitry in a first region of a semiconductor substrate; forming a first trench in a second region of the semiconductor substrate; filling the first trench with an epitaxial layer; forming a light source within a second trench formed in a first region of the epitaxial layer; forming a light detector within a third trench located in a second region of the epitaxial layer; depositing a dielectric layer over the semiconductor substrate, the dielectric layer covering the light source and the light detector; and forming a microfluidic flow channel within the dielectric layer. 10. The method of claim 9 , further comprising forming an interconnect layer between the dielectric layer and the semiconductor substrate. 11. The method of claim 9 , further comprising forming a light blocking layer within the epitaxial layer between the light source and the light detector. 12. The method of claim 9 , wherein the light source is formed by epitaxially growing a lower gallium nitride layer of a first conductivity type and an upper gallium nitride layer of a second conductivity type that is opposite the first conductivity type within the second trench. 13. The method of claim 9 , wherein the forming the microfluidic channel comprises etching a sacrificial layer formed on the dielectric layer. 14. The method of claim 12 , further comprising forming a seed layer on a bottom surface of the second trench prior to the epitaxially growing the lower gallium nitride layer. 15. The method of claim 14 , wherein the seed layer comprises aluminum nitride (AlN). 16. The method of claim 11 , wherein the light blocking layer comprises copper, silver or aluminum. 17. The method of claim 11 , wherein the forming the light blocking layer comprises: forming a trench into the epitaxial layer, wherein the trench is located between the light source and the light detector; and coating at least sidewalls of the trench with a light-blocking material. 18. The microfluidic device of claim 1 , further comprising a first spectral filter located over the light source, and a second spectral filter located over the light detector, wherein the first spectral filter and the second spectral filter are laterally surrounded by the dielectric layer. 19. A microfluidic device comprising: an integrated circuitry located in a semiconductor substrate; a light source located in a first region of an epitaxial layer that is disposed over the semiconductor substrate; a light detector located in a second region of the epitaxial layer; and a microfluidic flow channel located within a dielectric layer that is disposed over the semiconductor substrate. 20. The microfluidic device of claim 19 , further comprising a first interconnect layer located between the epitaxial layer and the semiconductor substrate, and a second interconnect layer located between the epitaxial layer and the semiconductor substrate.

Assignees

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Classifications

  • microstructural devices · CPC title

  • characterised by the manufacture of the container or its components · CPC title

  • the analysis being performed on a sample stream · CPC title

  • Electrodes · CPC title

  • Measuring fluorescence of biological material, e.g. DNA, RNA, cells (G01N21/6428 takes precedence) · CPC title

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What does patent US9643181B1 cover?
A microfluidic system-on-a-chip includes signal processing, light generation and detection, and fluid handling functions formed on a single substrate. The disclosed integrated system has a smaller footprint than device structures where individual components are manufactured separately and then assembled. Moreover, the integrated system obviates alignment challenges associated with conventionall…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification B01L3/502715. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue May 09 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).