FIFO buffer system providing same clock cycle response to pop commands

Patent metadata

Field	Value
Publication number	US-9641464-B2
Application number	US-201213459841-A
Country	US
Kind code	B2
Filing date	Apr 30, 2012
Priority date	Apr 30, 2012
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A first-in first-out (FIFO) buffer system includes FIFO control logic and first and second storage partitions. Each storage partition includes a corresponding single-port memory bank and a prefetch buffer. The FIFO control logic alternates processing of PUSH commands between the first and second storage partitions. Additionally, the FIFO control logic anticipates POP commands based on the FIFO order and the alternating PUSH arrangement by initiating prefetches of data so that data to be accessed by a POP command is available at either the prefetch buffer (if the prefetch has completed) or the output of the single-port memory bank (if the prefetch has not yet completed) of the corresponding storage partition at the time the POP command is received, thereby enabling the output of the data for the POP command in the same clock cycle in which the POP command is received.

First claim

What is claimed is:

1. A first-in first-out (FIFO) buffer system comprising:
a first storage partition comprising a single-port memory bank having an input to receive a clock signal, the first storage partition associated with a first subset of memory addresses, the first storage partition further comprises a first prefetch buffer having an input to receive the clock signal;
a second storage partition comprising a single-port memory bank having an input to receive the clock signal, the second storage partition associated with a second subset of memory addresses; and
FIFO control logic coupled to the first and second storage partitions and having an input to receive the clock signal, in response to a read access for data being received by the FIFO control logic during a clock cycle of the clock signal, the FIFO control logic to access and output the data from the first storage partition in a same clock cycle of the clock signal in which the read access for the data is received and while a write access to the first storage partition is received in the same clock cycle of the clock signal, to determine the first prefetch buffer contains valid data in response to a prefetch of first data completing before the same clock cycle, and to determine the first prefetch buffer does not contain valid data in response to the prefetch of the first data not completing before the same clock cycle, to access and output the data from the first storage partition by accessing and outputting data from the first prefetch buffer in response to determining the first prefetch buffer is storing valid data and by accessing and outputting data available at an output of the single-port memory bank of the first storage partition in response to determining the first prefetch buffer is not storing valid data.

2. The FIFO buffer system of claim 1 , wherein the FIFO control logic is configured to select a selected one of the first and second storage partitions based on an alternating of read accesses between the first storage partition and the second storage partition.

3. The FIFO buffer system of claim 2 , wherein:
the first subset of memory addresses is even memory addresses and the second subset of memory addresses is odd memory addresses; and
the FIFO buffer system is to select the selected one of the first and second storage partitions based on whether a read address for the read access is an even address or an odd address.

4. The FIFO buffer system of claim 1 , wherein:
the second storage partition further comprises a second prefetch buffer having an input to receive the clock signal; and
the FIFO control logic is to prefetch data from the single-port memory bank of the first storage partition to the first prefetch buffer of the first storage partition and to prefetch data from the single-port memory bank of the second storage partition to the second prefetch buffer of the second storage partition.

5. The FIFO buffer system of claim 4 , wherein the FIFO control logic is configured to prefetch data from the single-port memory bank of the selected one of the first and second storage partitions by initiating a prefetch of data in a prior clock cycle of the clock signal in response to at least one of: a read access to the selected one of the first and second storage partitions during the prior clock cycle; and a read access or a write access to the other of the first and second storage partitions during the prior clock cycle and the prefetch buffer of the selected one of the first and second partitions not storing valid data during the prior clock cycle.

6. The FIFO buffer system of claim 4 , wherein the FIFO control logic is configured to receive a write access and store data associated with the write access to the selected one of the first and second storage partitions in the same clock cycle.

7. The FIFO buffer system of claim 6 , wherein the FIFO control logic is configured to store the data associated with the write access to the prefetch buffer of the selected one of the first and second storage partitions in response to the selected one of the first and second storage partitions being empty and to store the data associated with the write access to the single-port memory bank of the selected one of the first and second storage partitions.

8. In a first-in first-out (FIFO) buffer system, a method comprising:
alternating storage of data from PUSH commands between first and second storage partitions clocked by a clock signal, the first storage partition comprising a first single-port memory bank and a first prefetch buffer and the second storage partition comprising a second single-port memory bank and a second prefetch buffer; and
accessing and outputting data for a first POP command from one of the first and second storage partitions in the same clock cycle of the clock signal in which the first POP command is received at the FIFO buffer system while a first PUSH command corresponding to the one of the first and second storage partitions is received in the same clock cycle of the clock signal;
determining the first prefetch buffer contains valid data in response to a prefetch of first data completing before the same clock cycle; and
determining the first prefetch buffer does not contain valid data in response to the prefetch of the first data not completing before the same clock cycle, wherein accessing the first data from the first storage partition for output comprises:
accessing the first data from the first prefetch buffer for output in the third clock cycle in response to determining the first prefetch buffer contains valid data; and
accessing the first data from an output of the first single-port memory bank in the third clock cycle in response to determining the first prefetch buffer does not contain valid data.

9. The method of claim 8 , wherein alternating storage of data from PUSH commands comprises:
receiving the first PUSH command at the FIFO buffer system in a first clock cycle of the clock signal;
selecting the first storage partition for processing the first PUSH command based on a write address associated with the first PUSH command;
storing first data of the first PUSH command at the first single-port memory bank;
receiving a second PUSH command at the FIFO buffer system in a second clock cycle of the clock signal subsequent to the first clock cycle;
selecting the second storage partition for processing the second PUSH command based on a write address associated with the second PUSH command; and
storing second data of the second PUSH command at the second single-port memory bank.

10. The method of claim 9 , wherein accessing and outputting data for POP commands comprises:
initiating the prefetch of the first data from the first single-port memory bank to the first prefetch buffer prior to a third clock cycle of the clock signal, the third clock cycle subsequent to the first clock cycle;
receiving the first POP command at the FIFO buffer system in the third clock cycle;
selecting the first storage partition for processing the first POP command based on a read address associated with the first POP command; and
accessing the first data from the first storage partition for output from the FIFO buffer system in the third clock cycle.

11. The method of claim 8 , wherein prefetching the first data comprises:
initiating the prefetch of the first data from the first single-port memory bank during a fourth clock cycle of the clock signal prior to the third clock cycle.

12. The method of claim 10 , wherein accessing and outputting data for POP commands further comprises:
receiving a second POP command at the FIFO buffer system in a fourth clock cycle of the clock signal subs

Assignees

• Greenwood Robert T
• Bahary Robert
• Nxp Usa Inc

Inventors

• Greenwood Robert T
• Bahary Robert

Classifications

• H04L49/90 Primary

  Buffering arrangements · CPC title