System and method for dynamic frequency estimation for a spread-spectrum digital phase-locked loop

Patent metadata

Field	Value
Publication number	US-9641182-B2
Application number	US-201414169598-A
Country	US
Kind code	B2
Filing date	Jan 31, 2014
Priority date	Jan 31, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A digital phase-and-frequency controller. In one embodiment, the controller includes: (1) a first segment accumulator operable to accumulate errors while an accumulation-selection signal has a first value and (2) a second segment accumulator operable to accumulate errors while said accumulation-selection signal has a second value, and (3) circuitry operable to produce the control signal using the errors accumulated in the first segment accumulator while a use-selection signal has a first value and the errors accumulated in the second segment accumulator while the use-selection signal has a second value.

First claim

What is claimed is:

1. A digital phase-and-frequency controller, comprising:
a first segment accumulator operable to accumulate errors while an accumulation-selection signal has a first selection value;
a second segment accumulator operable to accumulate errors while said accumulation-selection signal has a second selection value; and
circuitry operable to produce a control signal using said errors accumulated in said first segment accumulator while a use-selection signal has a first value and said errors accumulated in said second segment accumulator while said use-selection signal has a second value,
wherein said accumulation-selection signal has said first selection value when a target frequency is ramping up and said second selection value when said target frequency is ramping down.

2. The digital phase-and-frequency controller as recited in claim 1 wherein said accumulation-selection and said use-selection signals are identical.

3. The digital phase-and-frequency controller as recited in claim 1 wherein said first and second accumulators are pre-programmed to initial values.

4. The digital phase-and-frequency controller as recited in claim 1 wherein said errors accumulated in said first segment accumulator and said errors accumulated in said second segment accumulator are nonlinear.

5. The digital phase-and-frequency controller as recited in claim 1 wherein said errors accumulated in said first segment accumulator and said errors accumulated in said second segment accumulator are bang-bang.

6. The digital phase-and-frequency controller as recited in claim 1 further comprising a frequency accumulator operable to multiply at least one of said errors accumulated in said first segment accumulator and said errors accumulated in said second segment accumulator by a gain.

7. A method of generating a digital control signal comprising:
accumulating errors in a first segment accumulator while an accumulation-selection signal has a first selection value;
accumulating errors in a second segment accumulator while said accumulation-selection signal has a second selection value; and
producing a control signal using said errors accumulated in said first segment accumulator while a use-selection signal has a first value and said errors accumulated in said second segment accumulator while said use-selection signal has a second value;
wherein said accumulation-selection signal has said first selection value when a target frequency is ramping up and said second selection value when said target frequency is ramping down.

8. The method as recited in claim 7 wherein said accumulation-selection and said use-selection signals are identical.

9. The method as recited in claim 7 further comprising pre-programming said first and second accumulators to initial values.

10. The method as recited in claim 7 wherein said errors accumulated in said first segment accumulator and said errors accumulated in said second segment accumulator are nonlinear.

11. The method as recited in claim 7 wherein said errors accumulated in said first segment accumulator and said errors accumulated in said second segment accumulator are bang-bang.

12. The method as recited in claim 7 further comprising multiplying at least one of said errors accumulated in said first segment accumulator and said errors accumulated in said second segment accumulator by a gain.

13. A digital spread-spectrum clock generator, comprising:
an oscillator;
a feedback loop; and
a phase-and-frequency controller including:
a first segment accumulator operable to accumulate errors while an accumulation-selection signal has a first selection value,
a second segment accumulator operable to accumulate errors while said accumulation-selection signal has a second selection value, and
circuitry operable to produce a control signal using said errors accumulated in said first segment accumulator while a use-selection signal has a first value and said errors accumulated in said second segment accumulator while said use-selection signal has a second value;

wherein said accumulation-selection signal has said first selection value when a target frequency is ramping up and said second selection value when said target frequency is ramping down.

14. The digital spread-spectrum clock generator as recited in claim 13 wherein said accumulation-selection and said use-selection signals are identical.

15. The digital spread-spectrum clock generator as recited in claim 13 wherein said first and second accumulators are pre-programmed to initial values.

16. The digital spread-spectrum clock generator as recited in claim 13 wherein said errors accumulated in said first segment accumulator and said errors accumulated in said second segment accumulator are nonlinear.

17. The digital spread-spectrum clock generator as recited in claim 13 wherein said errors accumulated in said first segment accumulator and said errors accumulated in said second segment accumulator are bang-bang.

18. The digital spread-spectrum clock generator as recited in claim 13 further comprising a frequency accumulator operable to multiply at least one of said errors accumulated in said first segment accumulator and said errors accumulated in said second segment accumulator by a gain.

19. The digital spread-spectrum clock generator as recited in claim 13 wherein said clock generator employs a phase interpolator.

20. The digital spread-spectrum clock generator as recited in claim 13 wherein said clock generator employs a multi-phase divider.

Assignees

• Nvidia Corp

Inventors

• Evans Kenneth

Classifications

• H03L7/081 Primary

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/1075

  by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence) · CPC title

• H03L7/0994

  comprising an accumulator · CPC title