Common N-well state retention flip-flop

Patent metadata

Field	Value
Publication number	US-9641160-B2
Application number	US-201514635849-A
Country	US
Kind code	B2
Filing date	Mar 2, 2015
Priority date	Mar 2, 2015
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

Embodiments include apparatuses, methods, and systems for state retention electronic devices. In embodiments, an electronic device may include a state retention flip-flop having a plurality of P-type metal oxide semiconductor (PMOS) devices coupled with a common N-well, with one or more of the plurality of PMOS devices powered by an always-on supply and one or more of the plurality of PMOS devices powered by a power-gated supply. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. An electronic device comprising:
a state retention flip-flop including P-type metal oxide semiconductor (PMOS) devices coupled with a common N-well, wherein one or more of the PMOS devices coupled with the common N-well are powered by an always-on supply and one or more of the PMOS devices coupled with the common N-well are powered by a power-gated supply.

2. The electronic device of claim 1 , wherein all PMOS devices in the state retention flip-flop are coupled with the common N-well and the common N-well is electrically coupled with the always-on supply.

3. The electronic device of claim 2 , wherein the state retention flip-flop includes a slave stage having a first AND-OR-Invert (AOI) gate and a second AOI gate, wherein the first AOI gate and the second AOI gate are powered by the always-on supply.

4. The electronic device of claim 2 , wherein the state retention flip-flop is a first state retention flip-flop in a first cell, wherein the electronic device further includes a second state retention flip-flop in a second cell adjacent to the first cell, and wherein the second state retention flip-flop includes PMOS devices coupled with the common N-well.

5. The electronic device of claim 4 , wherein the first state retention flip-flop includes a first inverter and a second inverter, and wherein the first inverter and the second inverter are cross coupled and powered by the always-on supply.

6. The electronic device of claim 4 , further comprising a local clock buffer having PMOS devices coupled with the common N-well, the local clock buffer coupled with the first state retention flip-flop and the second state retention flip-flop.

7. The electronic device of claim 6 , wherein the local clock buffer includes a device block powered by the always-on supply, an input terminal to receive a sleep state signal input, and an output terminal, and wherein the local clock buffer is to output a value of logic zero when the sleep state signal input indicates a sleep state is enabled.

8. The electronic device of claim 1 , wherein the state retention flip-flop is a master-slave state retention flip-flop, wherein a master stage of the master-slave state retention flip-flop includes devices powered by the power-gated supply, and wherein a slave stage of the master-slave state retention flip-flop includes devices powered by the always-on supply and one or more devices powered by the power-gated supply.

9. The electronic device of claim 8 , further comprising a local clock buffer, the local clock buffer including one or more devices powered by the always-on supply and one or more devices powered by the power-gated supply, wherein the common N-well is a first common N-well, and wherein the one or more devices of the local clock buffer powered by the always-on supply include a second common N-well coupled with PMOS components of the one or more devices powered by the always-on supply.

10. The electronic device of claim 9 , wherein the second common N-well is continuous with the first common N-well.

11. The electronic device of claim 1 , further comprising a processor, a memory coupled with the processor, and a display coupled with the processor, wherein the processor includes the state retention flip-flop.

12. An electronic circuit comprising:
a local clock buffer having a clock forcing component with a clock input terminal to receive a clock input signal, a sleep signal input terminal to receive a sleep state signal, and an output terminal; and
a state retention flip-flop having P-type metal oxide semiconductor (PMOS) devices coupled with a common N-well, wherein the local clock buffer is to provide a local clock signal to the state retention flip-flop, wherein the local clock buffer includes PMOS devices coupled with the common N-well, and wherein the local clock signal is set to a first logic state when the sleep state signal indicates a sleep state is enabled and the local clock signal toggles between the first logic state and a second logic state based at least in part on the clock input signal when the sleep state signal indicates the sleep state is not enabled.

13. The electronic circuit of claim 12 , wherein the state retention flip-flop includes:
a first clock inverter that is to receive the local clock signal and is to output an inverted local clock signal; and
a second clock inverter that is to receive the inverted local clock signal and is to output a twice inverted local clock signal.

14. The electronic circuit of claim 13 , wherein the first clock inverter is powered by an always-on supply and the second clock inverter is powered by a power-gated supply.

15. The electronic circuit of claim 12 , wherein the state retention flip-flop includes a master stage powered by a power-gated supply and a slave stage including a first AND-OR-Invert (AOI) gate powered by an always-on supply.

16. The electronic circuit of claim 15 , wherein the master stage includes master stage PMOS devices coupled with the common N-well and the slave stage includes slave stage PMOS devices coupled with the common N-well, and wherein the common N-well is coupled with the always-on supply.

17. The electronic circuit of claim 16 , wherein the slave stage includes a second AOI gate powered by the always-on supply.

18. An integrated circuit comprising:
layout rows; and
always-on voltage (VAON) cells disposed in a first layout row of the layout rows, wherein individual VAON cells of the VAON cells include one or more always-on devices, and wherein the VAON cells of the first layout row are coupled with a common N-well for P-type metal oxide semiconductor (PMOS) devices of the VAON cells.

19. The integrated circuit of claim 18 , wherein the common N-well is a continuous common N-well for all cells of the first layout row, and wherein the common N-well is electrically coupled with an always-on supply.

20. The integrated circuit of claim 19 wherein the layout rows further include a standard row that does not include a VAON cell, and wherein the standard row includes an N-well electrically coupled to a power-gated supply.

21. The integrated circuit of claim 20 , wherein all VAON cells of the integrated circuit, including VAON cells disposed in the first layout row, are disposed in no more than a predefined number of the layout rows.

22. The integrated circuit of claim 20 , wherein all VAON cells, including the VAON cells disposed in the first layout row, are disposed in a predefined section of the layout rows.

23. The integrated circuit of claim 18 , wherein the VAON cells in the first layout row are clustered in a block of adjoining VAON cells, wherein the common N-well extends across the block of adjoining VAON cells, and wherein the first layout row further includes one or more standard cells that are coupled with an N-well that is electrically coupled to a power-gated supply.

24. The integrated circuit of claim 18 , wherein the VAON cells include one or more state retention flip-flops, and wherein the VAON cells include a local clock buffer electrically coupled to provide a local clock signal to one or more of the one or more state retention flip-flops.

25. The integrated circuit of claim 24 , wherein the local clock buffer provides a local clock signal of a first logic state when a sleep state signal input to the local clock buffer indicates a sleep state is enabled.

Assignees

• Intel Corp

Inventors

• Agarwal Amit
• Hsu Steven
• Krishnamurthy Ram

Classifications

• H03K3/356008 Primary

  ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• H03K3/35625 Primary

  using complementary field-effect transistors · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K3/0372

  of the primary-secondary type · CPC title