Semiconductor device

Patent metadata

Field	Value
Publication number	US-9641102-B2
Application number	US-201514941721-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Dec 3, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first chip mounting part including a first portion and a second portion;
a second chip mounting part;
a third chip mounting part;
a first semiconductor chip mounted on the first portion of the first chip mounting part, and having a first power transistor;
a second semiconductor chip mounted on the second chip mounting part, and having a second power transistor;
a third semiconductor chip mounted on the second portion of the first chip mounting part, and having a third power transistor;
a fourth semiconductor chip mounted on the third chip mounting part, and having a fourth power transistor;
a first lead;
a second lead formed integrally with the second portion of the first chip mounting part;
a third lead;
a fourth lead formed integrally with the first portion of the first chip mounting part; and
a sealing member sealing the first chip mounting part to the third chip mounting part, the first semiconductor chip to the fourth semiconductor chip, a part of the first lead, a part of the second lead, a part of the third lead, and a part of the fourth lead, the sealing member including an upper surface, a lower surface positioned on an opposite side of the upper surface, a first side surface positioned between the upper surface and the lower surface in a thickness direction, and a second side surface facing the first side surface,
wherein the first chip mounting part to the third chip mounting part are arranged along a first direction in which the first side surface of the sealing member extends,
wherein the second chip mounting part is arranged between the first portion of the first chip mounting part and the second portion of the first chip mounting part when seen in a plan view,
wherein the second portion of the first chip mounting part is arranged between the second chip mounting part and the third chip mounting part when seen in a plan view,
wherein each of the first lead, the second lead, the third lead and the fourth lead includes a protruding portion protruding from the first side surface of the sealing member,
wherein the protruding portion of the second lead includes a part capable of being connected to a mounting substrate,
wherein a first rear surface electrode of the first semiconductor chip and a third rear surface electrode of the third semiconductor chip are electrically connected with each other via the first chip mounting part,
wherein a second rear surface electrode of the second semiconductor chip is electrically connected with the second chip mounting part,
wherein a fourth rear surface electrode of the fourth semiconductor chip is electrically connected with the third chip mounting part,
wherein a first front surface electrode of the first semiconductor chip and the second chip mounting part are electrically connected with each other via a first conductive member,
wherein a second front surface electrode of the second semiconductor chip and the first lead are electrically connected with each other via a second conductive member,
wherein a third front surface electrode of the third semiconductor chip and the third chip mounting part are electrically connected with each other via a third conductive member, and
wherein a fourth front surface electrode of the fourth semiconductor chip and the third lead are electrically connected with each other via a fourth conductive member.

2. The semiconductor device according to claim 1 ,
wherein the part capable of being connected to the mounting substrate is a part capable of being soldered with the mounting substrate.

3. The semiconductor device according to claim 1 ,
wherein the part capable of being connected to the mounting substrate is a part capable of being inserted into the mounting substrate.

4. The semiconductor device according to claim 1 ,
wherein a length of the protruding portion of the first lead, a length of the protruding portion of the second lead, and a length of the protruding portion of the third lead are equal to each other.

5. The semiconductor device according to claim 1 ,
wherein a heat capacity of the protruding portion of the second lead is larger than a heat capacity of the protruding portion of the first lead.

6. The semiconductor device according to claim 5 ,
wherein the protruding portion of the second lead has a first protruding portion and a second protruding portion which are spaced apart from each other.

7. The semiconductor device according to claim 6 ,
wherein a width of the first protruding portion in the first direction and a width of the second protruding portion in the first direction are equal to each other.

8. The semiconductor device according to claim 6 ,
wherein the first protruding portion of the second lead is arranged between the first lead and the second protruding portion of the second lead when seen in a plan view.

9. The semiconductor device according to claim 8 ,
wherein an interval in the first direction between the first lead and the first protruding portion of the second lead is equal to an interval in the first direction between the first protruding portion of the second lead and the second protruding portion of the second lead.

10. The semiconductor device according to claim 6 ,
wherein a part capable of being soldered with the mounting substrate is formed in the first protruding portion, and
wherein a part capable of being inserted into the mounting substrate is formed in the second protruding portion.

11. The semiconductor device according to claim 5 ,
wherein a width of the protruding portion of the second lead in the first direction is larger than a width of the protruding portion of the first lead in the first direction.

12. The semiconductor device according to claim 1 ,
wherein the first semiconductor chip is mounted on a rear surface of the first portion of the first chip mounting part,
wherein the second semiconductor chip is mounted on a rear surface of the second chip mounting part,
wherein the third semiconductor chip is mounted on a rear surface of the second portion of the first chip mounting part, and
wherein the fourth semiconductor chip is mounted on a rear surface of the third chip mounting part.

13. The semiconductor device according to claim 1 , further comprising:
a control unit controlling the first power transistor to the fourth power transistor; and
a plurality of control leads electrically connected with the control unit,
wherein each of the plurality of control leads protrudes from the second side surface of the sealing member.

14. The semiconductor device according to claim 1 ,
wherein each of the first power transistor to the fourth power transistor is an insulated gate bipolar transistor,
wherein each of the first rear surface electrode to the fourth rear surface electrode functions as a collector, and
wherein each of the first front surface electrode to the fourth front surface electrode functions as an emitter.

15. The semiconductor device according to claim 1 ,
wherein each of the first power transistor to the fourth power transistor is a field effect transistor,
wherein each of the first rear surface electrode to the fourth rear surface electrode functions as a drain, and
wherein each of the first front surface electrode to the fourth front surface electrode functions as a source.

16. The semiconductor device according to claim 1 ,
wherein the first portion is integrally formed with the second portion of the first chip mounting part.

17. The semiconductor device according to claim 1 ,
wherein

Assignees

• Renesas Electronics Corp

Inventors

• Mitamura Kazuhiro
• Bando Koji
• Sato Yukihiro
• Kanazawa Takamitsu

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title