Magnetic memory device and method of manufacturing the same

US9640755B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9640755-B2
Application numberUS-201514794801-A
CountryUS
Kind codeB2
Filing dateJul 8, 2015
Priority dateNov 10, 2014
Publication dateMay 2, 2017
Grant dateMay 2, 2017

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A magnetic memory device includes a reference magnetic pattern having a magnetization direction fixed in one direction, a free magnetic pattern having a changeable magnetization direction, and a tunnel barrier pattern disposed between the free and reference magnetic patterns. The free magnetic pattern has a first surface being in contact with the tunnel barrier pattern and a second surface opposite to the first surface. The magnetic memory device further includes a sub-oxide pattern disposed on the second surface of the free magnetic pattern, and a metal boride pattern disposed between the sub-oxide pattern and the second surface of the free magnetic pattern. The magnetization directions of the free and reference magnetic patterns are substantially perpendicular to the first surface of the free magnetic pattern.

First claim

Opening claim text (preview).

What is claimed is: 1. A memory device, comprising: a reference magnetic pattern having a magnetization direction fixed in one direction; a free magnetic pattern having a changeable magnetization direction; a tunnel barrier pattern disposed between the free magnetic pattern and the reference magnetic pattern, the free magnetic pattern having a first surface contacting the tunnel barrier pattern and a second surface opposite to the first surface; a sub-oxide pattern disposed on the second surface of the free magnetic pattern; and a tantalum boride pattern disposed between the sub-oxide pattern and the second surface of the free magnetic pattern, wherein the magnetization directions of the free and reference magnetic patterns are substantially perpendicular to the first surface of the free magnetic pattern. 2. The memory device of claim 1 , wherein the free magnetic pattern includes at least one magnetic element, and wherein a boride-formation energy of the tantalum boride pattern is lower than a boride-formation energy of the at least one magnetic element of the free magnetic pattern. 3. The memory device of claim 2 , wherein a boron concentration of the tantalum boride pattern is higher than a boron concentration of the free magnetic pattern. 4. The memory device of claim 3 , wherein at least a portion of the free magnetic pattern is in a crystalline state. 5. The memory device of claim 4 , wherein a boron concentration of the crystalline portion of the free magnetic pattern is lower than 10 at %. 6. The memory device of claim 1 , wherein the tantalum boride pattern further includes oxygen. 7. The memory device of claim 1 , wherein the sub-oxide pattern includes tantalum. 8. The memory device of claim 1 , wherein a thickness of the tantalum boride pattern is in a range of about 0.5 Åto about 10 Å. 9. The memory device of claim 1 , wherein the reference magnetic pattern, the tunnel barrier pattern, the free magnetic pattern, the tantalum boride pattern, and the sub-oxide pattern are sequentially stacked on a substrate. 10. The memory device of claim 1 , wherein the sub-oxide pattern, the tantalum boride pattern, the free magnetic pattern, the tunnel barrier pattern, and the reference magnetic pattern are sequentially stacked on a substrate. 11. A method of manufacturing a memory device, the method comprising: sequentially forming a reference magnetic layer, a tunnel barrier layer, and a free magnetic layer on a substrate; forming a tantalum boride layer on the free magnetic layer; and forming a sub-oxide layer on the tantalum boride layer, wherein the reference magnetic layer has a magnetization direction fixed in one direction, wherein the free magnetic layer has a changeable magnetization direction, wherein the magnetization directions of the reference magnetic layer and the free magnetic layer are substantially perpendicular to a surface of the free magnetic layer contacting the tunnel barrier layer. 12. The method of claim 11 , wherein the free magnetic layer includes at least one magnetic element and boron, wherein forming the tantalum boride layer and forming the sub-oxide layer comprises: forming a tantalum layer on the free magnetic layer; diffusing boron atoms of the free magnetic layer into a lower portion of the tantalum layer by an annealing process to form the tantalum boride layer; and supplying oxygen into a remaining upper portion of the tantalum layer by an oxidation process to form the sub-oxide layer. 13. The method of claim 11 , wherein forming the tantalum boride layer and forming the sub-oxide layer comprise: depositing the tantalum boride layer on the free magnetic layer by a deposition process; and depositing the sub-oxide layer on the tantalum boride layer by a deposition process. 14. The method of claim 13 , further comprising: after depositing the sub-oxide layer, performing a thermal treatment process to diffuse oxygen atoms included in the sub-oxide layer to an interface between the tantalum boride layer and the free magnetic layer. 15. The method of claim 11 , wherein the free magnetic layer includes at least one magnetic element, and wherein a boride-formation energy of the tantalum layer is lower than a boride-formation energy of the at least one magnetic element of the free magnetic layer. 16. The method of claim 11 , wherein a boron concentration of the tantalum boride layer is higher than a boron concentration of the free magnetic layer. 17. A method of manufacturing a memory device, the method comprising: forming a sub-oxide layer on a substrate; forming a tantalum boride layer and a free magnetic layer that are sequentially stacked on the sub-oxide layer; forming a tunnel barrier layer on the free magnetic layer; and forming a reference magnetic layer on the tunnel barrier layer, wherein the reference magnetic layer has a magnetization direction fixed in one direction, wherein the free magnetic layer has a changeable magnetization direction, and wherein the magnetization directions of the reference magnetic layer and the free magnetic layer are substantially perpendicular to a surface of the free magnetic layer contacting the tunnel barrier layer. 18. The method of claim 17 , wherein the free magnetic layer includes at least one magnetic element and boron, wherein forming the tantalum boride layer and the free magnetic layer comprises: forming a tantalum layer on the sub-oxide layer; forming the free magnetic layer on the tantalum layer; and diffusing boron atoms of the free magnetic layer into the tantalum layer by an annealing process to form the tantalum boride layer. 19. The method of claim 17 , wherein forming the tantalum boride layer and the free magnetic layer comprises: depositing the tantalum boride layer on the sub-oxide layer by a deposition process; and forming the free magnetic layer on the deposited tantalum boride layer. 20. The method of claim 19 , further comprising: after forming the free magnetic layer, performing a thermal treatment process to diffuse oxygen atoms included in the sub-oxide layer to an interface between the tantalum boride layer and the free magnetic layer.

Assignees

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Classifications

  • Electricity · mapped topic

  • Electricity · mapped topic

  • H01L43/12Primary

    Electricity · mapped topic

  • Materials of the active region · CPC title

  • details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

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What does patent US9640755B2 cover?
A magnetic memory device includes a reference magnetic pattern having a magnetization direction fixed in one direction, a free magnetic pattern having a changeable magnetization direction, and a tunnel barrier pattern disposed between the free and reference magnetic patterns. The free magnetic pattern has a first surface being in contact with the tunnel barrier pattern and a second surface oppo…
Who is the assignee on this patent?
Lee Joonmyoung, Kim Kwangseok, Kim Ki Woong, and 3 more
What technology area does this patent fall under?
Primary CPC classification H01L43/12. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 02 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).