Semiconductor devices including epitaxial layers and related methods

Patent metadata

Field	Value
Publication number	US-9640652-B2
Application number	US-201213608350-A
Country	US
Kind code	B2
Filing date	Sep 10, 2012
Priority date	Mar 27, 2009
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A semiconductor device may include a semiconductor layer having a first conductivity type, a well region of a second conductivity type in the semiconductor layer wherein the first and second conductivity types are different, and a terminal region of the first conductivity type in the well region. An epitaxial semiconductor layer may be on the surface of the semiconductor layer including the well region and the terminal region with the epitaxial semiconductor layer having the first conductivity type across the well and terminal regions. A gate electrode may be on the epitaxial semiconductor layer so that the epitaxial semiconductor layer is between the gate electrode and portions of the well region surrounding the terminal region at the surface of the semiconductor layer.

First claim

That which is claimed is:

1. A semiconductor device comprising:
a semiconductor layer having a first conductivity type;
a well region of a second conductivity type in the semiconductor layer wherein the first and second conductivity types are different;
a terminal region of the first conductivity type in the well region;
an epitaxial semiconductor layer on a surface of the semiconductor layer including the well region and the terminal region wherein the epitaxial semiconductor layer has the first conductivity type on the terminal region and portions of the well region surrounding the terminal region at the surface of the semiconductor layer, and wherein the epitaxial semiconductor layer extends across an entirety of the well region and the terminal region at the surface of the semiconductor layer;
a gate electrode on the epitaxial semiconductor layer so that the epitaxial semiconductor layer is between the gate electrode and portions of the well region surrounding the terminal region at the surface of the semiconductor layer; and
an ohmic contact on the epitaxial semiconductor layer, wherein the epitaxial semiconductor layer includes a terminal contact region of the first conductivity type therethrough providing electrical contact between the ohmic contact and the terminal region, and wherein the epitaxial semiconductor layer includes a well contact region of the second conductivity type therethrough providing electrical contact between the ohmic contact and the well region;
wherein the ohmic contact includes a first metal layer on the terminal contact region and on the well contact region, a second metal layer on a portion of the first metal layer opposite the well contact region, and a silicon layer on a portion of the first metal layer opposite the terminal contact region surrounding the second metal layer.

2. The semiconductor device of claim 1 wherein the ohmic contact comprises a first ohmic contact, the device further comprising:
a second ohmic contact on the semiconductor layer so that the semiconductor layer is between the first ohmic contact and the second ohmic contact.

3. The semiconductor device of claim 1 wherein the epitaxial semiconductor layer has a dopant concentration of less than about 1×10 17 cm −3 outside the terminal contact region and outside the well contact region.

4. A semiconductor device comprising:
a semiconductor layer having a first conductivity type;
a well region of a second conductivity type in the semiconductor layer wherein the first and second conductivity types are different;
a terminal region of the first conductivity type in the well region;
an epitaxial semiconductor layer on a surface of the semiconductor layer including the well region and the terminal region wherein the epitaxial semiconductor layer has the first conductivity type on the terminal region and portions of the well region surrounding the terminal region at the surface of the semiconductor layer, and wherein the epitaxial semiconductor layer extends across an entirety of the well region and the terminal region at the surface of the semiconductor layer;
a gate electrode on the epitaxial semiconductor layer so that the epitaxial semiconductor layer is between the gate electrode and portions of the well region surrounding the terminal region at the surface of the semiconductor layer; and
an ohmic contact on the epitaxial semiconductor layer, wherein the epitaxial semiconductor layer includes a terminal contact region of the first conductivity type therethrough providing electrical contact between the ohmic contact and the terminal region, and wherein the epitaxial semiconductor layer includes a well contact region of the second conductivity type therethrough providing electrical contact between the ohmic contact and the well region;
wherein an outer edge of the terminal contact region throughout a thickness of the epitaxial semiconductor layer is set back from an outer edge of the terminal region around a perimeter of the terminal region;
wherein the ohmic contact includes a first metal layer on the terminal contact region and on the well contact region, a second metal layer on a portion of the first metal layer opposite the well contact region, and a silicon layer on a portion of the first metal layer opposite the terminal contact region surrounding the second metal layer.

5. The semiconductor device of claim 1 further comprising:
a gate insulating layer between the gate electrode and the epitaxial semiconductor layer.

6. The semiconductor device of claim 1 wherein the epitaxial semiconductor layer has a thickness in the range of about 1200 Angstroms to about 1800 Angstroms.

7. The semiconductor device of claim 1 wherein the epitaxial semiconductor layer has a first surface adjacent the semiconductor layer and a second surface remote from the semiconductor layer, and wherein the first and second surfaces of the epitaxial semiconductor layer are substantially planar.

8. A semiconductor device comprising:
a semiconductor layer having a first conductivity type;
a well region of a second conductivity type in the semiconductor layer wherein the first and second conductivity types are different;
a terminal region of the first conductivity type in the well region;
an epitaxial semiconductor layer on a surface of the semiconductor layer including the well region and the terminal region wherein the epitaxial semiconductor layer has a thickness in the range of about 1200 Angstroms to about 1800 Angstroms, and wherein the epitaxial semiconductor layer extends across an entirety of the well region and the terminal region at the surface of the semiconductor layer;
a gate electrode on the epitaxial semiconductor layer so that the epitaxial semiconductor layer is between the gate electrode and portions of the well region surrounding the terminal region at the surface of the semiconductor layer; and
an ohmic contact on the epitaxial semiconductor layer, wherein the epitaxial semiconductor layer includes a terminal contact region of the first conductivity type therethrough providing electrical contact between the ohmic contact and the terminal region, and wherein the epitaxial semiconductor layer includes a well contact region of the second conductivity type therethrough providing electrical contact between the ohmic contact and the well region;
wherein the ohmic contact includes a first metal layer on the terminal contact region and on the well contact region, a second metal layer on a portion of the first metal layer opposite the well contact region, and a silicon layer on a portion of the first metal layer opposite the terminal contact region surrounding the second metal layer.

9. The semiconductor device of claim 8 wherein the ohmic contact comprises a first ohmic contact, the device further comprising:
a second ohmic contact on the semiconductor layer so that the semiconductor layer is between the first ohmic contact and the second ohmic contact.

10. A semiconductor device comprising:
a semiconductor layer having a first conductivity type;
a well region of a second conductivity type in the semiconductor layer wherein the first and second conductivity types are different;
a terminal region of the first conductivity type in the well region;
an epitaxial semiconductor layer on a surface of the semiconductor layer including the well region and the terminal region wherein the epitaxial semiconductor layer has a thickness in the range of about 1200 Angstroms to about 1800 Angstroms;
a gate electrode on the epitaxial semiconductor layer so that the epitaxial semiconductor layer is between the gate electrode and portions of the well region surrounding the terminal region at the surface of the sem

Assignees

• Hull Brett Adam
• Zhang Qingchun
• Cree Inc

Inventors

• Hull Brett Adam
• Zhang Qingchun

Classifications

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/151 Primary

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/107

  Buried supplementary regions, e.g. buried guard rings  (multi-RESURF H10D62/111) · CPC title

• H10D30/635 Primary

  having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs · CPC title