Display apparatus

Patent metadata

Field	Value
Publication number	US-9640601-B2
Application number	US-201614988119-A
Country	US
Kind code	B2
Filing date	Jan 5, 2016
Priority date	Jan 8, 2015
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A display apparatus including a pixel including a first thin-film transistor (TFT) and a second TFT connected to the first TFT, the display apparatus includes a substrate, a semiconductor layer disposed on the substrate and including an active region of the first TFT and an active region of the second TFT, a first gate layer disposed on the semiconductor layer and including a gate of the first TFT and a gate of the second TFT, a second gate layer disposed on the first gate layer and including a connection node connecting the gate of the first TFT to the active region of the second TFT, and a line layer disposed on the second gate layer and configured to supply a driving voltage to the pixel.

First claim

What is claimed is:

1. A display apparatus comprising a pixel comprising a first thin-film transistor (TFT) and a second TFT connected to the first TFT, the display apparatus comprising: a substrate;
a semiconductor layer disposed on the substrate, the semiconductor layer comprising an active region of the first TFT and an active region of the second TFT;
a first gate layer disposed on the semiconductor layer, the first gate layer comprising a gate of the first TFT and a gate of the second TFT;
a second gate layer disposed on the first gate layer, the second gate layer comprising a connection node connecting the gate of the first TFT to the active region of the second TFT; and
a capacitor comprising a lower electrode and an upper electrode,
wherein:
the lower electrode comprises the gate of the first TFT; and
the upper electrode comprises a portion of the second gate layer.

2. The display apparatus of claim 1 , further comprising:
a first insulating layer disposed between the semiconductor layer and the first gate layer; and
a second insulating layer disposed between the first gate layer and the second gate layer.

3. The display apparatus of claim 1 , wherein the second gate layer comprises the upper electrode.

4. The display apparatus of claim 3 , wherein:
the connection node comprises a contact region connected to the gate of the first TFT through a first contact plug; and
the contact region is surrounded by the upper electrode, the upper electrode at least partially having a U-shape in a plan view.

5. The display apparatus of claim 1 , further comprising a fourth insulating layer disposed between the second gate layer and a line layer.

6. The display apparatus of claim 1 , further comprising:
a pixel electrode disposed on a line layer to overlap the first TFT, the second TFT, the capacitor, and the connection node; and
a fifth insulating layer disposed between the line layer and the pixel electrode.

7. The display apparatus of claim 1 , wherein the connection node is connected to the active region of the second TFT through a second contact plug, and the second TFT connects the first TFT.

8. A display apparatus comprising a pixel comprising a first thin-film transistor (TFT), a second TFT connected to the first TFT, and a capacitor, the display apparatus comprising:
a substrate;
a semiconductor layer disposed on the substrate, the semiconductor layer comprising an active region of the first TFT and an active region of the second TFT;
a first gate layer disposed on the semiconductor layer, the first gate layer comprising a gate of the first TFT and a gate of the second TFT; and
a second gate layer disposed on the first gate layer, the second gate layer comprising a connection node connecting the gate of the first TFT to the active region of the second TFT,
wherein:
the capacitor comprises a lower electrode and an upper electrode;
the lower electrode comprises the gate of the first TFT; and
the upper electrode comprises a portion of the second gate layer.

9. The display apparatus of claim 8 , further comprising:
a first insulating layer disposed between the semiconductor layer and the first gate layer; and
a second insulating layer disposed between the first gate layer and the second gate layer.

10. The display apparatus of claim 8 , further comprising a line layer disposed on the second gate layer, the line layer configured to supply a driving voltage to the pixel.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Hyunyoung

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H01L27/1222

  Electricity · mapped topic

• H01L27/124

  Electricity · mapped topic