Method of manufacturing a magnetoresistive memory device

Patent metadata

Field	Value
Publication number	US-9640584-B2
Application number	US-201514645239-A
Country	US
Kind code	B2
Filing date	Mar 11, 2015
Priority date	Oct 2, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

According to one embodiment, a magnetoresistive memory device, includes a metal buffer layer provided on a substrate, a crystalline metal nitride buffer layer provided on the metal buffer layer, and a magnetoresistive element provided on the metal nitride buffer layer. The metal nitride buffer layer and the metal buffer layer contain a same material.

First claim

What is claimed is:

1. A method of manufacturing a magnetoresistive memory device, the method comprising:
forming a metal buffer layer on a substrate;
forming a metal nitride buffer layer on the metal buffer layer by nitriding the metal buffer layer;
forming a magnetoresistive element comprising a magnetic layer on the metal nitride buffer layer; and
etching the magnetoresistive element selectively up to the metal buffer layer.

2. The method of claim 1 , wherein the metal buffer layer is crystalline.

3. The method of claim 1 , wherein the metal nitride buffer layer and the metal buffer layer contain a same material.

4. The method of claim 3 , wherein the nitriding the metal buffer layer is to execute thermal treatment in an atmosphere containing N radical.

5. The method of claim 3 , wherein the nitriding the metal buffer layer is to execute thermal treatment in a reactive gas atmosphere containing N and H, or N and O.

6. The method of claim 1 , wherein the forming the metal buffer layer and the forming the magnetoresistive element are executed by sputtering.

7. The method of claim 1 , wherein the magnetoresistive element is formed by sandwiching a nonmagnetic layer between the magnetic layers.

8. The method of claim 1 , wherein the metal buffer layer contains at least one of Nb, Mo and Hf.

9. The method of claim 1 , wherein
the substrate comprises a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, and a bottom electrode buried in the interlayer insulating film, and
the interlayer insulating film is formed on the semiconductor substrate before forming the metal buffer layer and, further, the bottom electrode is buried in the contact hole after forming a contact hole in the interlayer insulating film.

10. The method of claim 9 , wherein the forming the metal buffer layer is to form the metal buffer layer on the bottom electrode.

11. The method of claim 9 , further comprising:
forming a select transistor on the semiconductor substrate,
wherein the forming the contact hole is to form a contact hole for connection to one of a source and a drain of the select transistor.

Assignees

• Nagamine Makoto
• Eeh Youngmin
• Ueda Koji
• Watanabe Daisuke
• Sawada Kazuya
• Nagase Toshihiko
• Toshiba Kk

Inventors

• Nagamine Makoto
• Eeh Youngmin
• Ueda Koji
• Watanabe Daisuke
• Sawada Kazuya
• Nagase Toshihiko

Classifications

• H01L43/12

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H01L27/228 Primary

  Electricity · mapped topic

• H10N50/10

  Magnetoresistive devices · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title