Vertical memory device with gate lines at the same level connected

Patent metadata

Field	Value
Publication number	US-9640549-B2
Application number	US-201414534181-A
Country	US
Kind code	B2
Filing date	Nov 6, 2014
Priority date	Nov 19, 2013
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a substrate;
a plurality of channels extending in a first direction which is vertical to a top surface of the substrate;
a plurality of gate lines stacked in the first direction to be spaced apart from each other and extending in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels, wherein the plurality of gate lines form a stepped structure in which, for a plurality of vertical levels, all gate lines of a first set of consecutive gate lines at a first vertical level are shorter than all gate lines of a second set of consecutive gate lines at a second vertical level lower than the first vertical level, the second set of consecutive gate lines vertically overlapping the first set of consecutive gate lines;
a plurality of gate line cut patterns extending in the second direction between neighboring gate lines of the plurality of gate lines;
a connecting portion which connects a group of consecutive gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of consecutive gate lines extend, and including connecting pieces between gate lines of the group of gate lines, wherein the gate line cut patterns are blocked by the connecting pieces in the stepped structure; and
a contact connected to the group of gate lines and adjacent to the connecting portion,
wherein the connecting portion is inside outermost ends of all gate lines of the group of consecutive gate lines in the second direction and is integral with the group of consecutive gate lines.

2. The vertical memory device of claim 1 , wherein the substrate includes a cell region and an extension region at a lateral portion of the cell region, and
wherein the connecting portion is disposed on the extension region.

3. The vertical memory device of claim 2 , wherein a plurality of the connecting portions are provided at different vertical levels and overlap each other in the first direction.

4. The vertical memory device of claim 2 , wherein the extension region includes a first extension region and a second extension region at both lateral portions of the cell region, and
wherein the plurality of gate lines are stacked in the first direction such that top surfaces of the plurality of gate lines are exposed alternately on the first extension region and the second extension region.

5. The vertical memory device of claim 4 , wherein a plurality of contacts are arranged alternately on the first extension region and the second extension region.

6. The vertical memory device of claim 1 , wherein the plurality of gate lines include ground selection lines (GSLs), word lines, and string selection lines (SSLs), and
wherein the SSLs at the same vertical level are separated from each other, and insulated from each other by the gate line cut patterns.

7. The vertical memory device of claim 6 , wherein the GSLs at the same vertical level are insulated from each other.

8. The vertical memory device of claim 6 , wherein the group of gate lines connected by the connecting portion includes a group of word lines of the word lines.

9. The vertical memory device of claim 1 , wherein the plurality of gate line cut patterns are formed in a respective one of a plurality of openings extending through the stepped structure.

10. The vertical memory device of claim 9 , wherein the plurality of openings extend in the second direction, and are blocked by the connecting pieces.

11. The vertical memory device claim 1 , wherein the contact is directly on the connecting portion.

12. The vertical memory device claim 1 , wherein channels of the plurality of the channels are arranged in the second direction to form a channel row,
wherein a plurality of channel rows are arranged in a third direction perpendicular to the second direction, and
wherein a gate line surrounds channels of the channel row.

13. A vertical memory device, comprising:
a substrate;
a plurality of channels extending in a first direction which is vertical to a top surface of the substrate;
a plurality of sets of gate lines stacked in the first direction, each set of gate lines including a group of consecutive gate lines at a same vertical level and extending in a second direction perpendicular to the first direction, the group of consecutive gate lines parallel to each other and separated from each other in a third direction perpendicular to the first direction and different from the second direction,
wherein the gate lines are defined by a plurality of openings extending in the second direction,
wherein each gate line of each group of consecutive gate lines intersects channels of the plurality of channels, and
wherein the plurality of sets of gate lines form a stepped structure which includes a plurality of vertical levels wherein, for each vertical level, each gate line of the set of gate lines at that vertical level has a shorter length than each gate line of the set of gate lines at a lower vertical level; and

at least a first connecting portion connecting consecutive gate lines of a first gate line group of the plurality of groups of gate lines, the connecting portion integrally formed to connect the consecutive gate lines of the first gate line group and extending in an extension direction different from the second direction,
wherein some of the plurality of openings are blocked by the first connecting portion; and
wherein the first connecting portion is inside outermost ends of all the consecutive gate lines of the first gate line group in the second direction.

14. The vertical memory device of claim 13 , wherein:
the plurality of channels are formed at a central region of the vertical memory device; and
the first connecting portion is formed in an outer region of the vertical memory device where the channels are not formed.

15. The vertical memory device of claim 14 , further comprising:
at least a second connecting portion connecting consecutive gate lines of a second gate line group of the plurality of groups of gate lines, the second gate line group at a different vertical level from the first gate line group, the second connecting portion integrally formed to connect the consecutive gate lines of the second gate line group and extending in the extension direction different from the second direction,
wherein the second connecting portion vertically overlaps the first connecting portion.

16. The vertical memory device of claim 13 , further comprising:
a word line contact shared among the consecutive gate lines of the first gate line group.

17. A vertical memory device, comprising:
a substrate including:
a cell region; and
a first extension region and a second extension region at opposite lateral portions of the cell region;

a plurality of cell blocks on the substrate, each cell block including:
a plurality of channels extending in a first direction which is vertical to a top surface of the substrate;
a plurality of gate lines, each gate line surrounding outer sidewalls of a set of channels of the plurality of channels and extending in a second, lengthwise direction perpendicular to the first direction, the plurality of gate lines including at least two groups of gate lines of the plurality of gate lines, the groups stacked in the first direction to be spaced apart from each other, wherein a length in the second direction of each gate line of a first group of consecutive gate line

Assignees

• Lee Seok-Won
• Lee Joon-Hee
• Eun Dong-Seog
• Lee Chang-Hyun
• Samsung Electronics Co Ltd

Inventors

• Lee Seok-Won
• Lee Joon-Hee
• Eun Dong-Seog
• Lee Chang-Hyun

Classifications

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C8/14 Primary

  Word line organisation; Word line lay-out · CPC title

• H01L27/11548

  Electricity · mapped topic

• H01L29/7889

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic