Non-volatile memory devices including vertical NAND channels and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9640545-B2
Application number	US-201414171074-A
Country	US
Kind code	B2
Filing date	Feb 3, 2014
Priority date	Feb 10, 2009
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A non-volatile memory device can include a plurality of immediately adjacent offset vertical NAND channels that are electrically coupled to a single upper select gate line or to a single lower select gate line of the non-volatile memory device.

First claim

What is claimed:

1. A non-volatile memory device comprising:
a plurality of vertical NAND channels electrically coupled to a same single select gate line of the non-volatile memory device;
bit line contacts on the vertical NAND channels; and
a bit line electrically connected to one of the vertical NAND channels through one of the bit line contacts,
wherein the bit line contacts are coupled to the same single select gate line; and
wherein a line defined by the bit line contacts comprises at least one turn.

2. A device according to claim 1 , wherein each of the vertical channels is controlled by control gates, the control gates being vertically stacked.

3. A device according to claim 2 , further comprising a tunnel insulation layer, a charge storage layer, and a block insulation layer,
wherein the tunnel insulation layer, the charge storage layer, and the block insulation layer are provided between the vertical channels and the control gate.

4. A device according to claim 3 , wherein at least one of the tunnel insulation layer, the charge storage layer and the block insulation layer extend onto upper and lower surfaces of the control gate.

5. A non-volatile memory device comprising:
a plurality of vertical NAND channels disposed vertically through a same single select gate line of the non-volatile memory device, the same single select gate line extending in a first direction;
bit line contacts on the vertical NAND channels;
a first bit line electrically connected to a first channel of the vertical NAND channels through a first bit line contact of the bit line contacts, the first bit line extending in a second direction; and
a second bit line electrically connected to a second channel of the vertical NAND channels through a second bit line contact of the bit line contacts, the second bit line extending in the second direction,
wherein the first bit line contact and the second bit line contact are disposed such that an imaginary line connecting a center of the first bit line contact and a center of the second bit line contact extends in a slanting direction with respect to the first direction and the second direction, the first direction and the second direction being substantially perpendicular.

6. The memory device according to claim 5 , wherein each of the vertical NAND channels is controlled by control gates, the control gates being vertically stacked.

7. The memory device according to claim 6 , further comprising a tunnel insulation layer, a charge storage layer, and a block insulation layer, wherein the tunnel insulation layer, the charge storage layer, and the block insulation layer are provided between each vertical NAND channel and each control gate.

8. The memory device according to claim 7 , wherein at least one of the tunnel insulation layer, the charge storage layer and the block insulation layer extend onto upper and lower surfaces of each control gate.

9. The memory device according to claim 5 , wherein the first bit line and the second bit line are immediately adjacent.

10. A non-volatile memory device comprising:
a plurality of vertical NAND channels disposed vertically through a same single select gate line of the non-volatile memory device, the same single select gate line extending in a first direction;
bit line contacts on the vertical NAND channels;
a first bit line contact of the bit line contacts contacting a first channel of the vertical NAND channels and a first bit line extending in a second direction;
a second bit line contact of the bit line contacts contacting a second channel of the vertical NAND channels,
wherein the first bit line contact and the second bit line contact are disposed such that an imaginary line connecting a center of the first bit line contact and a center of the second bit line contact extends in a slanting direction with respect to the first direction and the second direction, the first direction and the second direction being substantially perpendicular.

11. The memory device according to claim 10 , further comprising a second bit line extending in the second direction, wherein the second bit line contact contacts the second bit line.

12. The memory device according to claim 10 , wherein each of the vertical NAND channels is controlled by control gates, the control gates being vertically stacked.

13. The memory device according to claim 12 , further comprising a tunnel insulation layer, a charge storage layer, and a block insulation layer, wherein the tunnel insulation layer, the charge storage layer, and the block insulation layer are provided between each vertical NAND channel and each control gate.

14. The memory device according to claim 13 , wherein at least one of the tunnel insulation layer, the charge storage layer and the block insulation layer extend onto upper and lower surfaces of each control gate.

15. A non-volatile memory device comprising:
a plurality of vertical NAND channels disposed vertically through a same single select gate line of the non-volatile memory device; and
bit line contacts disposed on the vertical NAND channels,
wherein a first group of the bit line contacts are disposed in a first row and a second group of the bit line contacts are disposed in a second row, the first and second rows are spaced apart in a column direction.

16. The memory device according to claim 15 , wherein the first group of the bit line contacts is shifted from the second group of the bit line contacts in a direction of the first and second rows.

17. The memory device according to claim 15 , wherein each of the vertical NAND channels is controlled by control gates, the control gates being vertically stacked.

18. The memory device according to claim 17 , further comprising a tunnel insulation layer, a charge storage layer, and a block insulation layer, wherein the tunnel insulation layer, the charge storage layer, and the block insulation layer are provided between each vertical NAND channel and each control gate.

19. The memory device according to claim 18 , wherein at least one of the tunnel insulation layer, the charge storage layer and the block insulation layer extend onto upper and lower surfaces of each control gate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seol Kwang Soo
• Kim Sukpil
• Park Yoondong

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G11C16/0408 Primary

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title

• H01L27/11556

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic