Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression

Patent metadata

Field	Value
Publication number	US-9640533-B2
Application number	US-201514656412-A
Country	US
Kind code	B2
Filing date	Mar 12, 2015
Priority date	Mar 12, 2015
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.

First claim

What is claimed is:

1. A method, comprising:
forming a set of fins of a first transistor, said set of fins comprising a first outer fin, an inner fin, and a second outer fin;
performing an oxide deposition process for depositing an oxide material upon said set of fins and within spaces between said fins;
performing a first recess process for removing a portion of the oxide material, leaving a portion of the oxide material on inside walls of said first and second outer fins;
performing a spacer nitride deposition process for depositing a spacer nitride material upon said set of fins and on outer walls of the first and second outer fins;
preforming a spacer nitride removal process, leaving spacer nitride material on a first portion at the outer walls of the first and second outer fins;
performing a second recess process for removing said oxide material from the inside walls of said first and second outer fins; and
performing an epitaxial layer deposition process upon said set of fins and said outer walls of said first and second outer fins, wherein any lateral over-growth of epitaxial layer on said outer walls of said first and second outer fins is suppressed by said spacer nitride material at the first portion, and wherein lateral overgrowth of the epitaxial layer occurs on a second portion of the outer walls of said first and second outer fins.

2. The method of claim 1 , wherein forming said epitaxial layer comprises performing at least one of a reduced pressure CVD (RPCVD), ultra-high vacuum CVD (UHVCVD), metal organic CVD (MOCVD).

3. The method of claim 1 , wherein forming said epitaxial layer upon comprises providing a precursor selected from the group consisting of SiH 4 gas, Si 2 H 4 Cl 2 gas, Si 2 H 6 gas, Si 3 H 8 gas and GeH 4 gas.

4. The method of claim 1 , wherein performing said first recess process comprises performing an SiCoNi etch process.

5. The method of claim 1 , wherein said performing said epitaxial layer deposition process further comprises forming said epitaxial layer upon a third outer fin of a second transistor adjacent to said first transistor, such that said epitaxial layer on said first outer fin does not touch said epitaxial layer deposited on said third outer fin.

6. The method of claim 1 , wherein performing said oxide deposition process comprises depositing silicon dioxide.

7. The method of claim 1 , wherein performing said spacer nitride deposition process comprises depositing silicon nitride.

8. The method of claim 1 , wherein at least a portion of any vertical over-growth of said epitaxial layers on said outer walls of said first and second outer fins is suppressed by said spacer nitride material.

Assignees

• Globalfoundries Inc

Inventors

• Lim Kwan-Yong
• Prindle Christopher Michael

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L27/0886 Primary

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic