Multi-die package with bridge layer and method for making the same

Patent metadata

Field	Value
Publication number	US-9640521-B2
Application number	US-201514588715-A
Country	US
Kind code	B2
Filing date	Jan 2, 2015
Priority date	Sep 30, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A package structure includes a substrate having a first bond pad layer. A silicon bridge layer having one or more redistribution layers therein. The silicon bridge layer has a second bond pad, and the silicon bridge layer is attached to the substrate by an adhesive layer. A first die is coupled to the substrate and the silicon bridge layer. A second die is coupled to the silicon bridge layer, wherein the first die and the second die communicate with one another by way of the one or more redistribution layers. Power and/or ground connectors are coupled to the first bond pad and the second bond pad for enabling grounding and/or transferring power from the semiconductor substrate to the second die.

First claim

What is claimed is:

1. A package comprising:
a semiconductor substrate having a first bond pad;
a silicon bridge layer having one or more redistribution layers therein, the silicon bridge layer having a second bond pad, the silicon bridge layer being attached to the semiconductor substrate by an adhesive layer;
a first die coupled to the semiconductor substrate and the silicon bridge layer, the first die overlying a sidewall of the silicon bridge layer;
a second die coupled to the silicon bridge layer, wherein the first die and the second die communicate with one another by way of the one or more redistribution layers; and
power and/or ground connectors coupled to the first bond pad and the second bond pad for enabling grounding and/or transferring power from the semiconductor substrate to the second die, wherein the first bond pad is positioned on the semiconductor substrate so it is outside of a lateral extent of the silicon bridge layer.

2. The package of claim 1 , wherein the adhesive layer comprises a die attachment film (DAF), an epoxy, or a glue.

3. The package of claim 1 , further comprising an isolation layer on sides and a portion of a top surface of the silicon bridge layer to electrically isolate the silicon bridge layer from the power and/or ground connectors, and wherein the isolation layer comprises a polyimide, molding compound, epoxy, MUF material, or combinations thereof.

4. The package of claim 1 , wherein the first die comprises a logic die and the second die comprises a memory die, and further wherein the memory die comprises a Dynamic Random Access Memory (DRAM) die, Static Random Access Memory (SRAM) die, hybrid memory (HBM) cube die, or combinations thereof.

5. The package of claim 1 , wherein the power and/or ground connectors comprise bond wires.

6. The package of claim 1 , wherein the power and/or ground connectors comprise solder bumps or solder balls.

7. The package of claim 1 , wherein the first die is electrically coupled to the semiconductor substrate and the silicon bridge layer by a plurality of copper pillars or copper posts.

8. The package of claim 1 , wherein the second die is electrically coupled to the silicon bridge layer by a plurality of copper pillars or copper posts.

9. The package of claim 1 , wherein a first underfill is disposed between the first die and a portion of the semiconductor substrate and between the first die and a first portion of the silicon bridge layer and a second underfill between the second die and a second portion of the silicon bridge layer, opposite the first portion of the silicon bridge layer.

10. A package structure comprising:
a semiconductor substrate having at least one first bond pad thereon;
a silicon bridge layer having one or more redistribution layers disposed therein, the silicon bridge layer attached to the semiconductor substrate, the silicon bridge layer having at least one second bond pad thereon, and further the silicon bridge layer having a layer of protective coating on a surface thereof but exposing the at least one second bond pad;
a first chip coupled to the semiconductor substrate by a plurality of conductive pillars and to the silicon bridge layer by a first plurality of conductive bumps;
a second chip coupled to the silicon bridge layer by a second plurality of conductive bumps, the second chip communicating with the first chip by way of the one or more redistribution layers;
power and/or ground connectors connected between the at least one first bond pad and the at least one second bond pad for enabling grounding and/or transferring power from the semiconductor substrate to the second chip, the power and/or ground connectors being external to the silicon bridge layer and contacting a sidewall of the silicon bridge layer; and
a first underfill disposed between the first chip and a portion of the semiconductor substrate and between the first chip and a first portion of the silicon bridge layer, and a second underfill disposed between the second chip and a second portion of the silicon bridge layer, opposite the first portion of the silicon bridge layer.

11. The package structure of claim 10 , wherein the layer of protective coating comprises a polyimide, molding compound, epoxy, MUF material, or combinations thereof.

12. The package structure of claim 10 , wherein the first chip comprises a logic chip and the second chip comprises a memory chip and further wherein the second chip comprises a Dynamic Random Access Memory (DRAM) die, Static Random Access Memory (SRAM) die, hybrid memory (HBM) cube die, or combinations thereof.

13. The package structure of claim 10 , wherein the power and/or ground connectors comprise bond wires.

14. The package structure of claim 10 , wherein the power and/or ground connectors comprise solder bumps or solder balls.

15. A package comprising:
a plurality of first connectors on a top surface of a substrate;
a bridge layer attached to the substrate, the bridge layer having one or more redistribution layers therein;
a plurality of second connectors on a top surface of the bridge layer, the plurality of second connectors connected to the one or more redistribution layers;
a first die coupled to the substrate and the bridge layer, a first section of the first die overlying the bridge layer and a second section of the first die not overlying the bridge layer;
a second die coupled to the bridge layer, the one or more redistribution layers communicatively coupling the first die and the second die; and
at least one third connector coupled to at least one of the plurality of first connectors and at least one of the plurality of second connectors, the at least one third connector for enabling transferring of power from the substrate to the second die and/or grounding, the at least one third connector being external to the bridge layer and extending along a sidewall of the bridge layer.

16. The package of claim 15 , wherein the bridge layer is attached to the substrate by an adhesive layer.

17. The package of claim 15 , wherein the first die is coupled to the substrate by at least one fourth connector in contact with at least one of the plurality of first connectors, and wherein the first die is coupled to the bridge layer by at least one fifth connector in contact with at least one of the plurality of second connectors.

18. The package of claim 15 , wherein the second die is coupled to the bridge layer by at least one sixth connector in contact with at least one of the plurality of second connectors.

19. The package of claim 15 , wherein the at least one third connector comprises a solder bump, a solder ball, a conductive bump, or a conductive paste.

20. The package of claim 15 , further comprising an isolation layer on at least one surface of the bridge layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Wei Sen
• Chen Yu-Feng
• Chen Chen-Shien
• Lii Mirng-Ji

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title