Leadless electronic packages for GaN devices

Patent metadata

Field	Value
Publication number	US-9640471-B2
Application number	US-201615050338-A
Country	US
Kind code	B2
Filing date	Feb 22, 2016
Priority date	Feb 24, 2015
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

Leadless electronic packages for GaN-based half bridge power conversion circuits have low inductance internal and external connections, high thermal conductivity and a large separation between external connections for use in high voltage power conversion circuits. Some electronic packages employ “L” shaped power paths and internal low impedance die to die connections. Further embodiments employ an insulative substrate disposed within the electronic package for efficient power path routing and increased packaging density.

First claim

What is claimed is:

1. An integrated half-bridge component comprising:
a first semiconductor die mounted to a first die pad and including a first power transistor having a first source terminal and a first drain terminal, wherein the first source terminal is electrically coupled to the first die pad;
a second semiconductor die mounted to a second die pad and including a second power transistor having a second source terminal and a second drain terminal, wherein the second source terminal is electrically coupled to the second die pad;
an electrically insulative encapsulant formed around the first and the second semiconductor dies; and
wherein the integrated half-bridge component has an external ground connection formed by the first die pad, an external switch node connection formed by the second die pad and an external V in connection that is coupled to a drain of the second semiconductor die.

2. The integrated half-bridge component of claim 1 further comprising a gap having a distance of at least 1.5 mm disposed between the first die pad and the second die pad.

3. The integrated half-bridge component of claim 1 wherein the first and the second semiconductor dies are GaN-based.

4. The integrated half-bridge component of claim 1 wherein the first semiconductor die has a top surface including the first source and the first drain terminal and a bottom surface that is attached to the first die pad.

5. The integrated half-bridge component of claim 1 wherein the first drain terminal is electrically coupled to the second die pad.

6. The integrated half-bridge component of claim 5 further comprising power connections disposed on a bottom surface of the integrated half-bridge component including a ground connection, a switch node connection and a V in connection.

7. The integrated half-bridge component of claim 6 wherein the power connections are arranged in an “L” shaped pattern with the ground connection forming a first leg, the switch node connection forming a corner and the V in connection forming a second leg.

8. The integrated half-bridge component of claim 6 wherein the power connections are arranged in a linear pattern wherein the ground connection is followed by the switch node connection that is followed by the V in connection.

9. The integrated half-bridge component of claim 1 wherein the first semiconductor die includes a first level shift circuit that is electrically coupled to a level shift receiver terminal on the second semiconductor die.

10. The integrated half-bridge component of claim 9 wherein the level shift receiver terminal is coupled to a signal modulator that is coupled to a second power transistor drive circuit.

11. The integrated half-bridge component of claim 9 wherein the first level shift circuit is coupled to a gate drive terminal on the second semiconductor die using a die to die wirebond.

12. The integrated half-bridge component of claim 11 wherein the die to die wirebond is formed using a bond stitch on ball attachment.

13. An electronic power conversion component comprising:
an electrically conductive package base comprising a plurality of leads and first and second die pads;
a first GaN-based die having a top surface opposite a bottom surface, wherein the bottom surface is attached to the first die pad and wherein the top surface includes a first power transistor having a first source terminal and a first drain terminal, wherein the first source terminal is electrically coupled to the first die pad;
a second GaN-based die having a top surface opposite a bottom surface, wherein the bottom surface is attached to the second die pad and wherein the top surface includes a second power transistor having a second source terminal and a second drain terminal, wherein the second source terminal is electrically coupled to the second die pad;
one or more conductors electrically coupling at least one of the plurality of leads to the first GaN-based die; and
an encapsulant formed over the first and second GaN-based dies and at least a top surface of the electrically conductive package base.

14. The electronic power conversion component of claim 13 further comprising a third die including a control circuit electrically coupled to the first GaN-based die, and attached to the first die pad.

15. An electronic component comprising:
a first lead, a second lead and a third lead;
a first GaN-based semiconductor die having a bottom surface opposite a top surface, wherein the bottom surface is mounted to the first lead and the top surface includes a first power transistor having a first source terminal, a first drain terminal and a first input terminal, and wherein the first source terminal is electrically coupled to the first lead, the first drain terminal is coupled to the second lead and the first input terminal is coupled to the third lead.

16. The electronic component of claim 15 wherein a plurality of wirebonds electrically couple the first source terminal to the first lead.

17. The electronic component of claim 15 wherein the electronic package has a fourth lead that is a kelvin connection to the first source terminal.

18. An electronic power conversion component comprising:
an electrically conductive package base comprising a plurality of leads and a die pad;
a first GaN-based die secured to the die pad and including a first power transistor having a first source terminal and a first drain terminal, wherein the first source terminal is electrically coupled to the die pad;
an insulative substrate secured to the die pad and having an electrically conductive top surface;
a second GaN-based die secured to the electrically conductive top surface and including a second power transistor having a second source terminal and a second drain terminal, wherein the second source terminal is electrically coupled to the electrically conductive top surface;
a switch-node connection formed within the electronic power conversion component between the first drain terminal and the electrically conductive top surface; and
an encapsulant formed over the first and second GaN-based dies, the insulative substrate and at least a top surface of the electrically conductive package base.

19. The electronic power conversion component of claim 18 further comprising a third die secured to the die pad and including control circuitry configured to control the operation of the first and the second power transistors.

20. The electronic power conversion component of claim 18 further comprising a bootstrap capacitor disposed within the power conversion component and attached to the electrically conductive top surface of the insulative substrate.

Assignees

• Navitas Semiconductor Inc

Inventors

• Kinzer Daniel M

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title