Semiconductor device including a solder barrier

Patent metadata

Field	Value
Publication number	US-9640459-B1
Application number	US-201614987139-A
Country	US
Kind code	B1
Filing date	Jan 4, 2016
Priority date	Jan 4, 2016
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A semiconductor device includes a leadframe and a semiconductor chip including a contact. The contact faces the leadframe and is electrically coupled to the leadframe via solder. The semiconductor device includes a solder barrier adjacent to the first contact and an edge of the chip.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a leadframe;
a semiconductor chip comprising a contact, the contact facing the leadframe and electrically coupled to a surface of the leadframe via solder; and
a solder barrier adjacent to the contact and an edge of the semiconductor chip, the solder barrier disposed above the surface of the leadframe and at least partially between the semiconductor chip and the surface of the leadframe to prevent the solder from reaching the edge of the semiconductor chip during a solder reflow process.

2. The semiconductor device of claim 1 , wherein the solder barrier is on the leadframe.

3. The semiconductor device of claim 1 , wherein the solder barrier is on the semiconductor chip.

4. The semiconductor device of claim 1 , wherein the solder barrier completely surrounds the edge of the chip.

5. The semiconductor device of claim 1 , wherein the solder barrier completely surrounds the contact.

6. The semiconductor device of claim 1 , wherein the solder barrier comprises a plated region.

7. The semiconductor device of claim 1 , wherein the solder barrier comprises an epoxy or imide region.

8. The semiconductor device of claim 1 , wherein the solder barrier comprises an oxide region.

9. A semiconductor device comprising:
a leadframe;
a chip comprising a first contact to a first semiconductor region of the chip on a first side of the chip and a second contact to a second semiconductor region of the chip on a second side of the chip opposite to the first side, the first contact adjacent an edge of the chip; and
a solder barrier extending from the first side of the chip between the first contact and the edge of the chip such that a solder short between the first contact and the second semiconductor region along the edge of the chip is prevented during solder reflow.

10. The semiconductor device of claim 9 , wherein the solder barrier comprises a plated region.

11. The semiconductor device of claim 9 , wherein the solder barrier comprises an epoxy or imide region.

12. The semiconductor device of claim 9 , wherein the solder barrier comprises an oxide region.

13. The semiconductor device of claim 9 , wherein the solder barrier laterally surrounds the first contact.

14. The semiconductor device of claim 13 , wherein the solder barrier is square shaped.

15. The semiconductor device of claim 13 , wherein the solder barrier is circle shaped.

16. The semiconductor device of claim 9 , wherein the solder barrier is L-shaped.

17. A semiconductor device comprising:
a leadframe having a major surface;
a semiconductor chip comprising a first contact on a first side of the chip, the first contact facing the leadframe and electrically coupled to the leadframe via solder; and
a solder barrier extending from the major surface of the leadframe, the solder barrier disposed at least partially between the leadframe and the semiconductor chip and laterally surrounding the semiconductor chip, the solder barrier to control bond line thickness.

18. The semiconductor device of claim 17 , wherein the solder barrier comprises a plated region.

19. The semiconductor device of claim 17 , wherein the solder barrier comprises an epoxy or imide region.

20. The semiconductor device of claim 17 , wherein the solder barrier comprises an oxide region.

Assignees

• Infineon Technologies Ag

Inventors

• Tay Wee Boon
• Woo Kuan Ching
• Calo Paul Armand

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W70/457

  of metallic layers on leadframes · CPC title