Methods of forming interconnects and semiconductor structures

Patent metadata

Field	Value
Publication number	US-9640433-B2
Application number	US-201414176547-A
Country	US
Kind code	B2
Filing date	Feb 10, 2014
Priority date	Sep 2, 2004
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
selectively forming nickel over a tungsten material on a substrate without forming the nickel over one or more of an aluminum material and a copper material on the substrate;
activating the aluminum material or the copper material to nickel plating; and
forming nickel over an exposed surface of the aluminum material or the copper material.

2. The method of claim 1 , wherein selectively forming nickel over a tungsten material on a substrate without forming the nickel over one or more of an aluminum material and a copper material comprises:
exposing the substrate to a palladium(II) solution to activate the tungsten material without activating the aluminum material or the copper material; and
exposing the substrate to a nickel plating solution.

3. The method of claim 1 , wherein forming nickel over an exposed surface of the aluminum material or copper material comprises:
exposing the substrate to a zincate solution to activate the aluminum material or the copper material; and
exposing the substrate to a nickel plating solution.

4. The method of claim 1 , wherein selectively forming nickel over a tungsten material on a substrate without forming the nickel over one or more of an aluminum material and a copper material on the substrate comprises forming the nickel over an exposed tungsten lining without forming the nickel over an exposed aluminum bond pad or an exposed copper bond pad.

5. A method of forming an interconnect in a semiconductor structure, comprising:
removing a portion of a semiconductor substrate to form a via at least partially extending therethrough, the semiconductor substrate having at least one metal structure comprising at least one of aluminum and copper disposed thereon;
forming tungsten over surfaces exposed within the via;
selectively forming nickel over the tungsten within the via without forming nickel over the at least one of aluminum and copper of the at least one metal structure;
activating the at least one of aluminum and copper of the at least one metal structure to nickel plating; and
forming nickel over an exposed surface of the at least one of aluminum and copper of the at least one metal structure.

6. The method of claim 5 , further comprising filling the remaining portions of the via with solder.

7. The method of claim 5 , further comprising forming at least one of an oxide material and an adhesion material over surfaces exposed within the via before forming the tungsten.

8. The method of claim 5 , wherein forming tungsten over surfaces exposed within the via comprises lining the surfaces exposed within the via with the tungsten.

9. The method of claim 5 , wherein forming tungsten over surfaces exposed within the via comprises forming tungsten over surfaces of at least one of a bond pad, an oxide material, and the semiconductor substrate exposed within the via.

10. The method of claim 5 , wherein selectively forming nickel over the tungsten within the via comprises:
activating the tungsten toward nickel plating without activating the at least one of aluminum and copper; and
exposing the tungsten to a nickel plating solution.

11. The method of claim 10 , wherein activating the tungsten toward nickel plating without activating the at least one of aluminum and copper comprises activating the tungsten by exposing the semiconductor structure to an aqueous solution comprising palladium(II) ions.

12. The method of claim 11 , further comprising exposing the tungsten to an aqueous potassium hydroxide solution before activating the tungsten toward the nickel plating.

13. The method of claim 5 , wherein selectively forming nickel over the tungsten comprises exposing the tungsten over the surfaces exposed within the via to a nickel plating solution.

14. The method of claim 5 , further comprising exposing the at least one metal structure to an aqueous solution comprising sodium hydroxide and at least one of nitric acid and phosphoric acid.

15. A method of forming an interconnect, comprising:
forming tungsten over an oxide material lining surfaces within a via extending at least partially through a semiconductor substrate;
forming nickel on the tungsten within the via without forming nickel on at least one exposed bond pad comprising at least one of aluminum and copper;
activating the at least one exposed bond pad toward nickel plating;
forming nickel on the at least one exposed bond pad; and
filling the via with at least one conductive material.

16. The method of claim 15 , wherein forming tungsten over an oxide material lining surfaces within a via extending at least partially through a semiconductor substrate comprises forming the tungsten on a titanium nitride material overlying the oxide material.

17. The method of claim 15 , wherein forming nickel on the tungsten within the via without forming nickel on at least one exposed bond pad comprises:
exposing the semiconductor structure to a palladium(II) solution to activate the tungsten without activating the at least one exposed bond pad; and
exposing the semiconductor structure to a nickel plating solution.

18. The method of claim 17 , wherein the at least one exposed bond pad comprises aluminum, and wherein exposing the semiconductor structure to a palladium(II) solution to activate the tungsten without activating the at least one exposed bond pad comprises activating the tungsten without activating the aluminum.

19. The method of claim 15 , wherein forming nickel on the at least one exposed bond pad comprises:
exposing the semiconductor structure to a zincate solution to activate the at least one exposed bond pad; and
exposing the semiconductor structure to a nickel plating solution.

20. The method of claim 15 , further comprising removing a portion of the semiconductor substrate from a backside of the semiconductor structure to expose the via filled with the at least one conductive material.

21. A method of forming an interconnect in a semiconductor structure, comprising:
removing portions of each of a bond pad comprising at least one of aluminum and copper and a semiconductor substrate to form a via extending through the bond pad and at least partially into the semiconductor substrate;
forming an oxide material over surfaces exposed within the via;
forming tungsten over the oxide material;
contacting the tungsten with a nickel plating solution to form nickel over the tungsten without forming nickel over the bond pad;
activating the bond pad toward nickel plating;
contacting the activated bond pad with a nickel plating solution to form nickel over the activated bond pad; and
filling the via with a conductive material.

22. The method of claim 21 , wherein contacting the activated bond pad with a nickel plating solution to form nickel over the activated bond pad comprises nickel plating portions of the bond pad exposed through a passivation material.

Assignees

• Micron Technology Inc

Inventors

• Akram Salman
• Wark James M
• Hiatt William Mark

Classifications

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/0261

  characterised by the filling method or the material of the conductive fill · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10P14/46

  using a liquid · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title