Methods of forming semiconductor devices
US-2024387699-A1 · Nov 21, 2024 · US
Spin-on spacer materials for double- and triple-patterning lithography
US9640396B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9640396-B2 |
| Application number | US-65246410-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 5, 2010 |
| Priority date | Jan 7, 2009 |
| Publication date | May 2, 2017 |
| Grant date | May 2, 2017 |
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Abstract
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Novel double- and triple-patterning methods are provided. The methods involve applying a shrinkable composition to a patterned template structure (e.g., a structure having lines) and heating the composition. The shrinkable composition is selected to possess properties that will cause it to shrink during heating, thus forming a conformal layer over the patterned template structure. The layer is then etched to leave behind pre-spacer structures, which comprise the features from the pattern with remnants of the shrinkable composition adjacent the feature sidewalls. The features are removed, leaving behind a doubled pattern. In an alternative embodiment, an extra etch step can be carried out prior to formation of the features on the template structure, thus allowing the pattern to be tripled rather than doubled.
First claim
Opening claim text (preview).
We claim: 1. A method of forming a microelectronic structure, said method comprising: providing a precursor structure having a patterned surface, said patterned surface including at least one raised feature having first and second sidewalls and an upper surface, wherein said precursor structure further comprises a second raised feature that is below said at least one raised feature, said second raised feature having first and second sidewalls and an upper surface and said at least…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P76/4085Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9640396B2 cover?
- Novel double- and triple-patterning methods are provided. The methods involve applying a shrinkable composition to a patterned template structure (e.g., a structure having lines) and heating the composition. The shrinkable composition is selected to possess properties that will cause it to shrink during heating, thus forming a conformal layer over the patterned template structure. The layer is …
- Who is the assignee on this patent?
- Lin Qin, Puligadda Rama, Claypool James, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10P76/4085. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 02 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).