Memory system and operating method thereof

Patent metadata

Field	Value
Publication number	US-9640281-B1
Application number	US-201615250826-A
Country	US
Kind code	B1
Filing date	Aug 29, 2016
Priority date	Mar 28, 2016
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A memory system includes: a memory device including a plurality of blocks each block including a plurality of pages, suitable for performing an operation in response to a command and an address; and a controller suitable for determining whether a block in which a read fail has occurred is an open block including an unprogrammed page, performing a restoration operation for the unprogrammed page of the open block based on at least one of operation temperature information and a read count, when it is determined that the block in which the read fail has occurred is the open block, and generating the command for performing a read retry operation.

First claim

What is claimed is:

1. A memory system comprising:
a memory device including a plurality of blocks each block including a plurality of pages, suitable for performing an operation in response to a command and an address; and
a controller suitable for determining whether a block in which a read fail has occurred is an open block including an unprogrammed page, performing a restoration operation for the unprogrammed page of the open block based on at least one of operation temperature information and a read count, when it is determined that the block in which the read fail has occurred is the open block, and generating the command for performing a read retry operation,
wherein the controller generates the command for performing the restoration operation for the unprogrammed page when the read count of the open block is greater than or equal to a certain reference value.

2. The memory system according to claim 1 , wherein the controller generates the command for performing the restoration operation for the unprogrammed page when a difference between a temperature at a time at which data of a programmed page of the open block is written and a temperature at a time at which the data is read is greater than or equal to a given level.

3. The memory system according to claim 1 , wherein, in the case where, while program operations are performed in response successively inputted write commands, the read fail occurs when the read operation is performed in response to a read command for lately programmed page data,
the restoration operation is performed by programming data that is continuously inputted in response to the write commands, on the unprogrammed page of the open block.

4. The memory system according to claim 1 , wherein, in the case where, after program operations are completed, the read fail occurs while the read operation is performed in response to a read command, the restoration operation is performed by programming system data and data stored in a page buffer after the program operations, on the unprogrammed page of the open block.

5. The memory system according to claim 1 , wherein, in the case where, after power-on, the read fail occurs while the read operation is performed in response to a read command for a block in which a last program operation has been performed, the restoration operation is performed by programming dummy data on the unprogrammed page of the open block.

6. The memory system according to claim 1 , wherein the memory device comprises:
a memory cell array including a plurality of blocks; and
a peripheral circuit suitable for controlling operation of the memory cell array in response to the command and the address,
wherein the peripheral circuit comprises:
a temperature sensor suitable for measuring a temperature at a time at which data is programmed during a program operation and a temperature at a time at which the data is outputted during a read operation, and providing the operation temperature information.

7. The memory system according to claim 6 , wherein the peripheral circuit comprises:
an address decoder coupled to the memory cell array through word lines and suitable for decoding the address and selecting one of the word lines;
a read/write circuit coupled to the memory cell array through bit lines and suitable for reading data from the memory cell array by driving the bit lines or drive the bit lines according to data to be stored in the memory cell array;
a voltage supply unit suitable for supplying voltages required for operation of the memory device; and
a control logic suitable for controlling the address decoder, the read/write circuit and the voltage supply unit, in response to the command.

8. The memory system according to claim 7 ,
wherein, when the command for the restoration operation is inputted, the control logic performs an additional program operation for the unprogrammed page of the open block and controls the open block so that the open block is converted into a closed block, and
wherein, when the command for performing the read retry operation is inputted, the control logic performs the read retry operation by changing a read voltage level applied to the memory cell array, based on a read retry table, and performing at least one read operation.

9. The memory system according to claim 6 , wherein the memory cell array comprises:
a main region configured to store user data capable of being accessed by a user; and
a spare region configured to store the operation temperature information provided from the temperature sensor, open/closed block information about whether the corresponding block is a closed block in which program operations for all pages have been completed or an open block in which program operations for only some pages have been completed, and system data including the read count,
wherein, when power-on, the system data stored in the spare region is transmitted to the controller.

10. The memory system of claim 9 , wherein the controller comprises:
an error correction unit suitable for detecting error bits included in data read out during the read operation, and indicating the read fail when the number of detected error bits is greater than or equal to a correctable error bit threshold value;
a memory suitable for storing, when power-on, the operation temperature information, the open/closed block information and the read count that are transmitted from the spare region; and
a processor suitable for checking, when the read fail occurs, whether a block in which the read fail has occurred is an open block, based on the open/closed block information, and performing, when the corresponding block is an open block, the restoration operation for an unprogrammed page of the open block, based on at least one of the operation temperature information and the read count, and generating the command for performing the read retry operation,
wherein the controller controls a count of read retry operations performed in the open block so that the count is equal to or greater than a count of read retry operations performed in the closed block.

11. An operating method of a memory system including a memory device provided with a memory cell array including a plurality of blocks each of which includes a plurality of pages; and a controller suitable for generating a command and an address to control operation of the memory device, the operating method comprising:
detecting error bits included in data read out from the memory device during a read operation of the memory device;
indicating a read fail when the number of detected error bits is greater than or equal to a correctable error bit threshold value;
determining, when the read fail occurs, whether a block in which the read fail has occurred is an open block including an unprogrammed page;
performing, if it is determined that the block in which the read fail has occurred is the open block including the unprogrammed page, a restoration operation for the unprogrammed page, based on at least one of operation temperature information and a read count; and
performing a read retry operation.

12. The operating method according to claim 11 , wherein the performing the restoration operation for the unprogrammed page comprises:
performing the restoration operation for the unprogrammed page when a difference between a temperature at a time at which data of a programmed page of the open block is written and a temperature at a time at which the data is read is greater than or equal to a given level.

13. The operating method according to claim 11 , wherein the performing the restoration operation for the unprogrammed page comprises:
performing the

Assignees

• Sk Hynix Inc

Inventors

• Seo Yoon-Seong
• Jung Won-Jin

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/064

  Management of blocks · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title