Highly scalable single-poly non-volatile memory cell

Patent metadata

Field	Value
Publication number	US-9640262-B2
Application number	US-201514719342-A
Country	US
Kind code	B2
Filing date	May 22, 2015
Priority date	Jul 8, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.

First claim

What is claimed is:

1. A nonvolatile memory (NVM) cell, comprising:
a semiconductor substrate;
a first OD region and a second OD region;
an isolation region separating the first OD region from the second OD region, the isolation region having a trench depth;
a PMOS select transistor disposed on the first OD region;
a PMOS floating gate transistor serially connected to the select transistor and being disposed on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region;
a memory P well in the semiconductor substrate, wherein the memory P well overlaps with the first OD region and the second OD region, and wherein the memory P well has a junction depth that is deeper than the trench depth of the isolation region, and wherein the memory P well has a continuous well structure between the first OD region and the second OD region;
a memory N well in the memory P well, wherein the memory N well merely overlaps with the first OD region, and wherein the memory N well has a junction depth that is shallower than the trench depth of the isolation region; and
an N + pickup in the memory N well.

2. The NVM cell according to claim 1 , wherein the PMOS select transistor and the PMOS floating gate transistor commonly share the memory N well.

3. The NVM cell according to claim 1 , wherein the PMOS select transistor comprises a P + source doping region in the memory N well, a common P + doping region spaced apart from the p + source doping region, a select gate channel region near a main surface of the semiconductor substrate between the P + source doping region and the common P + doping region, a select gate overlying the select gate channel region, and a gate dielectric layer between the select gate and the select gate channel region.

4. The NVM cell according to claim 3 , wherein the P + source doping region is coupled to a source line SL.

5. The NVM cell according to claim 1 , wherein the PMOS floating gate transistor further comprises a common P + doping region on one side of the floating gate, a P + drain doping region on the other side of the floating gate, a floating gate channel region between the common P + doping region and the P + drain doping region, and a gate dielectric layer between the floating gate and the floating gate channel region.

6. The NVM cell according to claim 5 , wherein the P + drain doping region is coupled to a bit line BL.

7. The NVM cell according to claim 1 , wherein the PMOS floating gate transistor serves as a charge storage element of the NVM cell.

8. The NVM cell according to claim 1 further comprising a floating gate extension continuously extended from the floating gate to the second OD region and is adjacent to an erase gate (EG) region in the second OD region.

9. The NVM cell according to claim 8 , wherein the floating gate extension traverses the isolation region between the first OD region and the second OD region and partially overlaps with the second OD region to capacitively couple to the EG region.

10. The NVM cell according to claim 8 , wherein the EG region comprises a double diffused drain (DDD) region and an N + doping region in the DDD region.

11. The NVM cell according to claim 10 , wherein the DDD region is an N-type doping region.

12. The NVM cell according to claim 10 , wherein the N + doping region and the DDD region are electrically coupled to an erase line voltage (V EL ).

Assignees

• Ememory Technology Inc

Inventors

• Hsu Te-Hsun
• Li Chun-Hsiao
• Chen Hsuen-Wei

Classifications

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C17/16

  using electrically-fusible links · CPC title