Method and circuit for programming non-volatile memory cells of a volatile/non-volatile memory array

Patent metadata

Field	Value
Publication number	US-9640257-B2
Application number	US-201515110717-A
Country	US
Kind code	B2
Filing date	Jan 7, 2015
Priority date	Jan 10, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A memory array including: a first volatile memory cell including first and second cross-coupled inverters between first and second storage nodes; a first non-volatile memory cell including at least one resistive element that can be programmed to take one of at least two resistive states; and a control circuit adapted to couple the first non-volatile memory cell to the first and second storage nodes in order to generate a current for programming the resistive state of the at least one resistive element.

First claim

The invention claimed is:

1. A memory array comprising:
a first volatile memory cell having first and second inverters cross-coupled between first and second storage nodes, the first storage node being coupled to the first bit line and the second storage node being coupled to the second bit line;
a first non-volatile memory cell coupled between the first and second bit lines and having at least one resistive element programmable to have one of at least two resistive states; and
a control circuit adapted to couple the first non-volatile memory cell to the first and second storage nodes to generate a current for programming the resistive state of the at least one resistive element.

2. The memory array of claim 1 , wherein the at least one resistive element is programmable by the direction of current passed through it to have one of said at least two resistive states.

3. The memory array of claim 1 , wherein the first non-volatile memory cell comprises first and second input nodes, and wherein the control circuit is adapted to couple the first non-volatile memory cell to the first and second storage nodes by coupling the first input node to the first storage node and by coupling the second input node to the second storage node.

4. The memory array of claim 3 , wherein the non-volatile memory cell comprises a single resistive element coupled in series with a first transistor between the first and second input nodes.

5. The memory array of claim 4 , wherein the control circuit is adapted to couple the first non-volatile memory cell to the first and second storage nodes by activating said first transistor.

6. The memory array of claim 3 , wherein the non-volatile memory cell comprises:
a first resistive element coupled in series with a second transistor between the first input node and a first voltage level; and
a second resistive element coupled in series with a third transistor between the second input node and the first voltage level.

7. The memory array of claim 3 , wherein said first volatile memory cell comprises:
a fourth transistor coupled between said first storage node and the first input node of the non-volatile memory cell;
a fifth transistor coupled between said second storage node and the second input node of the non-volatile memory cell, wherein the control circuit is adapted to couple the first non-volatile memory cell to the first and second storage nodes by activating said fourth and fifth transistors.

8. The memory array of claim 7 , wherein:
the first input node is connected to the first bit line;
the second input node is connected to the second bit line;
the first storage node is coupled to the first bit line via said fourth transistor; and
the second storage node is coupled to the second bit line via said fifth transistor.

9. The memory array of claim 7 , wherein:
the first input node is connected to a first internal node;
the second input node is connected to a second internal node;
the first storage node is coupled to the first internal node via said fourth transistor;
the second storage node is coupled to the second internal node via said fifth transistor;
the first internal node is coupled to the first bit line via a sixth transistor;
the second internal node is coupled to the second bit line via a seventh transistor; and
the control circuit is adapted to deactivate the sixth and seventh transistors while coupling the first non-volatile memory cell to the first and second storage nodes.

10. The memory array of claim 9 , further comprising:
a second volatile memory cell having third and fourth inverters cross-coupled between third and fourth storage nodes, the third storage node being coupled to said first internal node and the fourth storage node being coupled to said second internal node via a ninth transistor; and
a second non-volatile memory cell having: at least one resistive element programmable to have one of at least two resistive states; a third input node connected to said first internal node; and a fourth input node connected to said second internal node.

11. The memory array of claim 1 , further comprising a read/write circuit adapted to read from the first non-volatile memory cell a programmed resistive state representing a first data bit and write the first data bit to the first volatile memory cell.

12. The memory array of claim 1 , wherein each of said volatile memory cells is coupled to a voltage supply rail coupled via a switch to a supply voltage level.

13. The memory array of claim 1 , wherein said at least one resistive element of each of said non-volatile memory cells is one of:
a spin transfer torque element with in-plane anisotropy;
a spin transfer torque element with perpendicular-to-plane anisotropy; and
a reduction oxide element.

14. A method of data back-up in the memory array of claim 1 , the method comprising:
coupling, by a control circuit, the first non-volatile memory cell to the first and second storage nodes to generate a current for programming the resistive state of the at least one resistive element.

15. A method of restoring data in the memory array of claim 1 , the method comprising:
reading from the first non-volatile memory cell a programmed resistive state representing a first data bit; and
writing the first data bit to the first volatile memory cell.

Assignees

• Commissariat L Energie Atomique Et Aux Energies Alternatives
• Centre Nat Rech Scient

Inventors

• Javerliac Virgile
• Layer Christophe

Classifications

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C14/0081

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title