Ring protocol for low latency interconnect switch

Patent metadata

Field	Value
Publication number	US-9639490-B2
Application number	US-201113994792-A
Country	US
Kind code	B2
Filing date	Nov 29, 2011
Priority date	Nov 29, 2011
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.

First claim

What is claimed is:

1. A system, comprising:
a main board having a plurality of Central Processing Unit (CPU) sockets,
a plurality of CPU's, each installed in a respective CPU socket and including a plurality of processor cores;
a plurality of CPU socket-to-socket interconnect links operatively coupled between the plurality of CPU sockets so as to form a CPU socket-to-socket ring interconnect;
wherein each CPU is further configured to facilitate communication between itself and each of the other CPUs by sending data via the plurality of CPU socket-to-socket interconnect links, and wherein each of the CPUs comprises a plurality of processor cores operatively coupled to respective ring stop nodes in a ring interconnect internal to each CPU.

2. The system of claim 1 , wherein each CPU is further configured to facilitate communication between itself and other CPU's using a packet-based protocol under which packetized data is transferred between CPU's via the plurality of CPU socket-to-socket interconnect links.

3. The system of claim 2 , wherein the packet-based protocol is the QuickPath Interconnect (QPI) protocol.

4. The system of claim 2 , wherein the plurality of processor cores in each CPU are operatively coupled to a memory controller and at least one coherency agent, wherein the memory controller and the at least once coherency agent are configured to manage access to memory operatively couplable to the memory controller, and wherein the packet-based protocol supports coherent memory transactions across CPU's.

5. The system of claim 1 , wherein at least one of the CPU's includes a first and second ring stop node operatively coupled to respective CPU socket-to-socket interconnect links, wherein the first and second ring stop nodes are separate from the respective ring stop nodes in the ring interconnect operative coupled to the plurality of processor cores.

6. The system of claim 1 , wherein at least one of the CPU's includes a single ring stop node operatively coupled to respective CPU socket-to-socket interconnect links, wherein the single ring stop node is separate from the respective ring stop nodes in the ring interconnect operative coupled to the plurality of processor cores.

7. The system of claim 6 , wherein at least one of the CPU's that includes a single ring stop node operatively coupled to respective CPU socket-to-socket interconnect links is configurable to enable data to be transferred via the respective CPU socket-to-socket interconnect links in a manner that bypasses the ring interconnect internal to the CPU.

8. The system of claim 6 , wherein the plurality of CPU's are configured to effect routing of packets between CPU's by inserting a packet at a first ring stop node on a first ring interconnect internal to a first CPU, routing the packet across a CPU socket-to-socket interconnect link to a second CPU, and routing the message to a component coupled to a second ring stop node on a second ring interconnect internal to the second CPU.

9. The system of claim 1 , wherein the system is configured to support coherent memory accesses under which a processor core in a first CPU is enabled to access memory managed via a memory controller in a second CPU that is not directly linked to the first CPU via a CPU socket-to-socket interconnect link between the first and second CPU's.

10. A method, comprising:
implementing a memory coherency protocol in a computer system having shared memory resources and including a plurality of Central Processing Units (CPU's) operatively coupled to one another via a plurality of CPU socket-to-socket ring interconnect links so as to form a CPU socket-to-socket ring interconnect, wherein a processor core in a first CPU is enabled to access a memory resources that are managed by memory controllers in other CPU's while supporting coherent memory transactions,
wherein each of the CPUs comprises a plurality of processor cores operatively coupled to respective ring stop nodes in a ring interconnect internal to each CPU.

11. The method of claim 10 , further comprising implementing a coherent memory transaction using packetized messages sent over a transfer path including at least two CPU socket-to-socket ring interconnect links.

12. The method of claim 11 , wherein the memory coherency protocol is the QuickPath Interconnect (QPI) protocol.

13. The method of claim 10 , wherein each CPU includes a ring interconnect and at least one CPU socket-to-socket ring interconnect link is configured to enable bypass of a ring interconnect, the method further comprising routing a message from a first CPU to a second CPU via a first socket-to-socket ring interconnect link between the first CPU and a third CPU and via a second socket-to-socket ring interconnect link between the third CPU and the second CPU, wherein the ring interconnect on the third CPU is bypassed.

14. A Central Processing Unit (CPU), comprising:
a plurality of pins or pads, configured to be coupled to a mating CPU socket of a main board to facilitate communication between the CPU and circuitry on the main board when the CPU is installed in the CPU socket;
a ring interconnect having a plurality of nodes including ring stop nodes;
a plurality of processor cores, each operatively coupled to a respective ring stop node; and
first and second interconnect interfaces operatively coupled to a single node or respective nodes, each interconnect interface coupled to a portion of the pins or pads corresponding to mating components in the CPU socket that are coupled to wires on the main board comprising first and second CPU socket-to-socket interconnect links,
wherein the CPU is further configured to be installed as one of a plurality of CPU's on a main board having a plurality of CPU sockets communicatively coupled via a plurality of CPU socket-to-socket interconnect links so as to form a CPU socket-to-socket ring interconnect, and further wherein the CPU is configured, when installed on the main board, to support communication between nodes on the CPU and nodes on another CPU coupled to the main board by transferring data via the first and second interconnect interfaces across CPU socket-to-socket interconnect links.

15. The CPU of claim 14 , wherein the CPU is further configured, when installed on the main board, to facilitate communication between itself and other CPU's installed on the main board using a packet-based protocol under which packetized data is transferred between CPU's via the plurality of CPU socket-to-socket interconnect links, wherein communications between the CPU and at least one other CPU traverses at least two CPU socket-to-socket interconnect links along the CPU socket-to-socket ring interconnect.

16. The CPU of claim 15 , wherein the plurality of processor cores are operatively coupled to a memory controller and at least one coherency agent, wherein the memory controller and the at least once coherency agent are configured to manage access to memory operatively couplable to the memory controller, and wherein the packet-based protocol supports coherent memory transactions across CPU's.

17. The CPU of claim 15 , wherein the CPU, when installed on the main board in a first CPU socket, is configured to effect routing of packets between itself and a second CPU installed on the main board in a second CPU socket linked in communication with the first CPU socket via a first socket-to-socket interconnect link by inserting a packet at a first node on the ring interconnect in the CPU, and routing the packet around the ring interconnect in the CPU to a second node in the CPU operatively coupled t

Assignees

• Blankenship Robert G
• Santhanakrishnan Geeyarpuram N
• Liu Yen-Cheng
• Fahim Bahaa
• Srinivasa Ganapati N
• Intel Corp

Inventors

• Blankenship Robert G
• Santhanakrishnan Geeyarpuram N
• Liu Yen-Cheng
• Fahim Bahaa
• Srinivasa Ganapati N

Classifications

• G06F17/13

  Differential equations (using digital differential analysers G06F7/64) · CPC title

• G06F13/4247

  on a daisy chain bus · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title