Provision of access control data within a data processing system

Patent metadata

Field	Value
Publication number	US-9639484-B2
Application number	US-201113881113-A
Country	US
Kind code	B2
Filing date	Sep 27, 2011
Priority date	Oct 26, 2010
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A data processing system ( 2 ) includes memory protection circuitry ( 10 ) storing access control data for controlling accesses to data at memory addresses within a main memory ( 16 ). An access control cache ( 14 ) may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry ( 10 ) to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache ( 14 ) is storing access control data for a memory access request, then the access control data stored within the access control cache ( 14 ) is used in place of access control data retrieved form the memory protection circuitry ( 10 ). In the first embodiment, access control data may be determined to be cachable is if is associated with a region of memory addresses within a plurality of hierarchically ordered memory addresses that is a highest order region which encompasses all the memory addresses within that region.

First claim

The invention claimed is:

1. Apparatus for processing data comprising:
memory protection circuitry configured to store access control data for a plurality of regions of memory address space within a memory, said plurality of regions having a hierarchical ordering there between, said memory protection circuitry:
(i) determining, in response to a memory access request to a target memory address received by said memory protection circuitry, a controlling region within said plurality of regions, said controlling region having a highest position within said hierarchical ordering of any of said plurality of regions encompassing said target address; and
(ii) returning access control data for said controlling region for controlling access to said memory by said memory access request; and
an access control cache coupled to said memory protection circuitry and configured to store access control data returned from said memory protection circuitry and to provide said access control data for said memory access request in place of said memory protection circuitry when said access control cache is storing said access control data for said memory access request,
wherein said memory protection circuitry when returning said access control data also generates:
(a) a cachability signal indicative of whether or not said access control data is eligible to be stored in said access control cache; and
(b) at least when said cachability signal indicates said access control data is eligible to be stored in said access control cache, address range defining signals for defining a range of memory address space within said memory for which said access control data controls access to said memory by memory access requests, and
wherein said memory protection circuitry:
generates said cachability signal with a value indicating said access control is eligible to be stored in said access control cache when said controlling region does not encompass any memory addresses that are encompassed within one or more other regions of said plurality of regions having a higher position within said hierarchical ordering than said controlling region; and
generates said cachability signal with a value indicating said access control is not eligible to be stored in said access control cache when said controlling region encompasses at least one memory address that is encompassed within one or more other regions of said plurality of regions having a higher position within said hierarchical ordering than said controlling region.

2. Apparatus as claimed in claim 1 , wherein said memory protection unit is configured to store cachability data for each region of said plurality of regions, said cachability data indicating of whether or not access control data for said region is eligible to be stored in said access control cache, said memory protection unit generating said cachability signal for said controlling region in dependence upon said cachability data for said controlling region.

3. Apparatus as claimed in claim 2 , wherein said memory protection circuitry includes analysis circuitry, said analysis circuitry determining said cachability data for each region of said plurality of regions.

4. Apparatus as claimed in claim 3 , wherein said analysis circuitry is powered down when not determining said cachability data.

5. Apparatus as claimed in claim 3 , wherein said analysis circuitry determines said cachability data asynchronously to said memory protection circuitry responding to received memory access requests.

6. Apparatus as claimed in claim 3 , wherein said analysis circuitry is a non-programmable finite state machine circuitry.

7. Apparatus as claimed in claim 3 , wherein said analysis circuitry compares each of region of said plurality of regions with, in turn, all other regions of said plurality of regions to determine said cachability data for said region.

8. Apparatus as claimed in claim 2 , wherein said access control cache is flushed whenever any of said access control data stored by said memory protection circuitry is written.

9. Apparatus for processing data comprising:
memory protection circuitry configured to store access control data for a plurality of regions of memory address space within a memory, said plurality of regions having a hierarchical ordering there between, said memory protection circuitry being configured to:
(i) determine, in response to a memory access request to a target memory address received by said memory protection circuitry, a controlling region within said plurality of regions, said controlling region having a highest position within said hierarchical ordering of any of said plurality of regions encompassing said target address; and
(ii) return access control data for said controlling region for controlling access to said memory by said memory access request; and
an access control cache coupled to said memory protection circuitry and configured to store access control data returned from said memory protection circuitry and to provide said access control data for said memory access request in place of said memory protection circuitry when said access control cache is storing said access control data for said memory access request;
wherein said memory protection circuitry when returning said access control data also generates:
(a) a cachability signal indicative of whether or not said access control data is eligible to be stored in said access control cache; and
(b) at least when said cachability signal indicates said access control data is eligible to be stored in said access control cache, address range defining signals for defining a range of memory address space within said memory for which said access control data controls access to said memory by memory access requests; and
wherein:
said plurality of regions include one or more non-contiguous regions, each non-contiguous region encompassing a plurality discrete ranges of memory addresses; and
said memory protection circuitry generates said cachability signal with a value indicating said access control is not eligible to be stored in said access control cache when said controlling region is a non-contiguous region.

10. Apparatus as claimed in claim 9 , wherein said cachability data is determined whenever any of said access control data stored by said memory protection circuitry is written.

11. Apparatus as claimed in claim 9 , wherein address defining signals specify one of:
(i) a base address of said controlling region and a size of said controlling region; and
(ii) a base address of said controlling region and a mask value for applying to a memory address to determine in conjunction with said base address if said memory address is within said controlling region.

12. Apparatus as claimed in claim 9 , comprising a cache memory configured to store program instructions from a main memory, said memory access request being a cache fetch from said main memory to said cache memory and said access control cache being coupled to said cache memory so as to provide said access control data for said cache fetch in place of said memory protection circuitry when said access control cache is storing said access control data for said cache fetch.

13. Apparatus as claimed in claim 9 , wherein said apparatus operates in a plurality of hardware modes and said access control data indicates for each region of said plurality of regions data specifying in which of said plurality of hardware modes a memory access request to a memory address within said region is permitted.

14. Apparatus as claimed in claim 9 , wherein said access control data indicates for each region of said plurality of regions data speci

Assignees

• Craske Simon John
• Teyssier Melanie Emanuelle Lucie
• Huot Nicolas Jean Phillippe
• Grandou Gilles Eric
• Advanced Risc Mach Ltd

Inventors

• Craske Simon John
• Teyssier Melanie Emanuelle Lucie
• Huot Nicolas Jean Phillippe
• Grandou Gilles Eric

Classifications

• G06F12/1441 Primary

  for a range · CPC title

• G06F12/1416 Primary

  by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights (G06F12/1458 takes precedence) · CPC title

• G06F12/145

  the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F12/1458

  by checking the subject access rights · CPC title