Managing event count reports in a tile-based architecture

Patent metadata

Field	Value
Publication number	US-9639367-B2
Application number	US-201314046249-A
Country	US
Kind code	B2
Filing date	Oct 4, 2013
Priority date	Oct 26, 2012
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

One embodiment of the present invention sets forth a graphics processing system configured to track event counts in a tile-based architecture. The graphics processing system includes a screen-space pipeline and a tiling unit. The screen-space pipeline includes a first unit, a count memory associated with the first unit, and an accumulating memory associated with the first unit. The first unit is configured to detect an event type and increment the count memory. The tiling unit is configured to cause the screen-space pipeline to update an external memory address to reflect a first value stored in the count memory when the first unit completes processing of a first set of primitives. The tiling unit is also configured to cause the screen-space pipeline to update the accumulating memory to reflect a second value stored in the count memory when the first unit completes processing of a second set of primitives.

First claim

What we claimed is:

1. A graphics processing system configured to track event counts in a tile-based architecture, the graphics processing system comprising:
a screen-space pipeline comprising:
a count memory,
a first unit configured to detect an event type and increment the count memory in response, and
an accumulating memory associated with the first unit;

a tiling unit configured to:
cause the screen-space pipeline to increment a value stored at an external memory address by a first value stored in the count memory when the first unit completes processing of a first set of primitives that overlap a first cache tile, and
cause the screen-space pipeline to update the accumulating memory to reflect a second value stored in the count memory when the first unit completes processing of a second set of primitives that overlap the first cache tile,

wherein at least one primitive in the first set of primitives and at least one primitive in the second set of primitives are configured to cause the first unit to detect the event type and increment the count memory.

2. The graphics processing system of claim 1 , wherein the tiling unit is further configured to receive a first plurality of primitives that includes the primitives in the first set of primitives, receive a second plurality of primitives that includes the primitives in the second set of primitives, determine that the first set of primitives overlaps the first cache tile, and determine that the second set of primitives overlaps the first cache tile.

3. The graphics processing system of claim 2 , wherein the tiling unit is further configured to receive a report request configured to request a final count value associated with the first plurality of primitives.

4. The graphics processing system of claim 3 , wherein the tiling unit is further configured to transmit the first set of primitives, the second set of primitives, and a first set of commands to the screen-space pipeline for processing, wherein the first set of commands includes a first command configured to cause the screen-space pipeline to increment the value stored at the external memory address after processing the first command.

5. The graphics processing system of claim 4 , wherein:
the first cache tile corresponds to an earliest cache tile associated with a render target; and
the first set of commands further includes a second command configured to cause the accumulating memory to store the second value stored in the count memory when the first unit completes processing of the second set of primitives.

6. The graphics processing system of claim 5 , wherein the first set of commands further includes a third command configured to cause the count memory to be reset after the second command is processed.

7. The graphics processing system of claim 4 , wherein:
the first cache tile corresponds to an intermediate cache tile associated with a render target; and
the first set of commands further includes a second command configured to cause the second value to be added to the accumulating memory when the first unit completes processing of the second set of primitives.

8. The graphics processing system of claim 7 , wherein the first set of commands further includes a third command configured to cause the count memory to be reset after the second command is processed.

9. The graphics processing system of claim 4 , wherein:
the first cache tile corresponds to a final cache tile associated with a render target;
the first set of commands further includes a second command configured to cause the second value to be added to the accumulating memory, when the first unit completes processing of the second set of primitives; and
the first set of commands further includes a third command configured to cause the count memory to store a value equal to a value stored in the accumulating memory after the second command is processed.

10. A computing device configured to track event counts in a tile-based architecture, the computing device comprising:
a graphics processing system comprising:
a screen-space pipeline comprising:
a count memory,
a first unit configured to detect an event type and increment the count memory in response, and
an accumulating memory associated with the first unit;

a tiling unit configured to:
cause the screen-space pipeline to increment a value stored at an external memory address by a first value stored in the count memory when the first unit completes processing of a first set of primitives that overlap a first cache tile, and
cause the screen-space pipeline to update the accumulating memory to reflect a second value stored in the count memory when the first unit completes processing of a second set of primitives that overlap the first cache tile,

wherein at least one primitive in the first set of primitives and at least one primitive in the second set of primitives are configured to cause the first unit to detect the event type and increment the count memory.

11. The computing device of claim 10 , wherein the tiling unit is further configured to receive a first plurality of primitives that includes the primitives in the first set of primitives, receive a second plurality of primitives that includes the primitives in the second set of primitives, determine that the first set of primitives overlaps the first cache tile, and determine that the second set of primitives overlaps the first cache tile.

12. The computing device of claim 11 , wherein the tiling unit is further configured to receive a report request configured to request a final count value associated with the first plurality of primitives.

13. The computing device of claim 12 , wherein the tiling unit is further configured to transmit the first set of primitives, the second set of primitives, and a first set of commands to the screen-space pipeline for processing, wherein the first set of commands includes a first command configured to cause the screen-space pipeline to increment the value stored at the external memory address after processing the first command.

14. The computing device of claim 13 , wherein:
the first cache tile corresponds to an earliest cache tile associated with a render target; and
the first set of commands further includes a second command configured to cause the accumulating memory to store the second value stored in the count memory when the first unit completes processing of the second set of primitives.

15. The computing device of claim 14 , wherein the first set of commands further includes a third command configured to cause the count memory to be reset after the second command is processed.

16. The computing device of claim 13 , wherein:
the first cache tile corresponds to an intermediate cache tile associated with a render target; and
the first set of commands further includes a second command configured to cause the second value to be added to the accumulating memory when the first unit completes processing of the second set of primitives.

17. The computing device of claim 16 , wherein the first set of commands further includes a third command configured to cause the count memory to be reset after the second command is processed.

18. The computing device of claim 13 , wherein:
the first cache tile corresponds to a final cache tile associated with a render target;
the first set of commands further includes a second command configured to cause the second value to be added to the accumulating memory, when the first unit completes processing of the second set of primitives; and
the first set of commands further

Assignees

• Nvidia Corp

Inventors

• Hakura Ziyad S
• Duluk Jr Jerome F

Classifications

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06T15/405

  using Z-buffer · CPC title

• G06F2212/302

  In image processor or graphics adapter · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title