Packed data rearrangement control indexes precursors generation processors, methods, systems, and instructions

US9639354B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9639354-B2
Application numberUS-201113977356-A
CountryUS
Kind codeB2
Filing dateDec 22, 2011
Priority dateDec 22, 2011
Publication dateMay 2, 2017
Grant dateMay 2, 2017

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes the result including a sequence of at least four non-negative integers. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: receiving an instruction, the instruction indicating a destination storage location and indicating a first numerical pattern defining parameter and a second numerical pattern defining parameter, the instruction not having an immediate, the first numerical pattern defining parameter to be used to evaluate a numerical pattern defining relation that is implicit to the instruction; and storing a result in the destination storage location in response to the instruction, the result including a sequence of at least four non-negative integers, the first numerical pattern defining parameter affecting a value of each of the at least four non-negative integers, wherein the second numerical pattern defining parameter also affects the value of each of the at least four non-negative integers, and wherein values of the at least four non-negative integers are not calculated using a result of a preceding instruction. 2. The method of claim 1 , wherein receiving comprises receiving the instruction that does not indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location. 3. The method of claim 1 , wherein receiving comprises receiving the instruction indicating an integer offset as the first numerical pattern defining parameter, and wherein storing comprises storing the sequence of the at least four non-negative integers with a smallest of the at least four non-negative integers differing from zero by the integer offset. 4. The method of claim 1 , wherein receiving comprises receiving the instruction indicating a constant integer stride as the first numerical pattern defining parameter, and wherein storing comprises storing the sequence of the at least four non-negative integers with all consecutive integers differing by the constant integer stride. 5. The method of claim 1 , wherein storing comprises storing the result including the sequence of at least thirty-two non-negative integers. 6. The method of claim 1 , further comprising accessing at least four non-negative integers from a non-architecturally visible storage location that is on-die with an execution unit that is executing the instruction and applying the first numerical pattern defining parameter to the at least four non-negative integers accessed from the non-architecturally visible storage location. 7. An apparatus comprising: a destination storage location; and an execution unit coupled with the destination storage location, the execution unit, in response to an instruction that is to indicate the destination storage location and is to indicate a first numerical pattern defining parameter that is to be used to evaluate a numerical pattern defining relation and is to indicate a second numerical pattern defining parameter, to store a result in the destination storage location, the result to include a sequence of at least four non-negative integers, wherein the first numerical pattern defining parameter is to affect a value of each of the at least four non-negative integers, wherein the second numerical pattern defining parameter is also to affect the value of each of the at least four non-negative integers, and wherein the execution unit is to store the result that is to include the sequence of the at least four non-negative integers without calculating values of the least four non-negative integers from a result of a preceding instruction. 8. The apparatus of claim 7 , wherein the execution unit is to store the result responsive to the instruction that is not to indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location. 9. The apparatus of claim 7 , wherein the instruction is to indicate an integer offset as the first numerical pattern defining parameter, and wherein the execution unit, in response to the instruction, is to store the sequence of the at least four non-negative integers with a smallest of the at least four non-negative integers to differ from zero by the integer offset. 10. The apparatus of claim 7 , wherein the instruction is to indicate a constant integer stride as the first numerical pattern defining parameter, and wherein the execution unit, in response to the instruction, is to store the sequence of the at least four non-negative integers with all consecutive integers to differ by the constant integer stride. 11. The apparatus of claim 7 , wherein the execution unit, in response to an opcode of the instruction, is to store all consecutive integers in the sequence of the at least four non-negative integers to differ by a constant stride. 12. An apparatus comprising: a destination storage location; a decode unit to decode an instruction that is to indicate the destination storage location, to indicate a first numerical pattern defining parameter, and to indicate a second numerical pattern defining parameter; and an execution unit coupled with the destination storage location and coupled with the decode unit, the execution unit, in response to the instruction, to store a result in the destination storage location, the result to include a sequence of at least four non-negative integers, wherein each of the first numerical pattern defining parameter and the second numerical pattern defining parameter are to affect a value of each of the at least four non-negative integers, and wherein the execution unit is to store the result that is to include the sequence of the at least four non-negative integers without calculating values of the least four non-negative integers from a result of a preceding instruction. 13. The apparatus of claim 12 , wherein the instruction is to indicate a constant integer stride as the first numerical pattern defining parameter, wherein the instruction is not to have an immediate, and wherein an opcode of the instruction is only capable of storing integers in numerical order.

Assignees

Inventors

Classifications

  • Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

  • G06F9/3001Primary

    Arithmetic instructions · CPC title

  • using stride · CPC title

  • Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

  • Bit or string instructions · CPC title

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What does patent US9639354B2 cover?
A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes the result including a sequence of at least four non-negative integers. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instru…
Who is the assignee on this patent?
Abraham Seth, Valentine Robert, Ould-Ahmed-Vall Elmoustapha, and 3 more
What technology area does this patent fall under?
Primary CPC classification G06F9/3001. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 02 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).