Method for manufacturing COA liquid crystal panel comprising color resist blocks having first and second intersection zones and COA liquid crystal panel

Patent metadata

Field	Value
Publication number	US-9638975-B2
Application number	US-201514758564-A
Country	US
Kind code	B2
Filing date	Apr 22, 2015
Priority date	Mar 18, 2015
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

The present invention provides a method for manufacturing a COA liquid crystal panel and a COA liquid crystal panel. The method includes forming a first pixel electrode layer on a color resist layer, forming a planarization layer on the first pixel electrode layer, and forming a second pixel electrode layer that is in engagement with the first pixel electrode layer on the planarization layer so as to achieve planarization of the pixel electrode layer to the maximum extent. Further, the second pixel electrode layer includes a pixel electrode block that is located in each sub pixel zone and has a lateral border located above a scan line and a longitudinal border located above a signal line so as to achieve self-shielding of light for the scan line and the signal line, allowing for omission of lateral and longitudinal black matrixes. Further, a dot-like black matrix is formed on a glass substrate at a location corresponding to a TFT on the array substrate to shield light for a site of a channel thereby simplifying the manufacturing process and increase the aperture ratio.

First claim

What is claimed is:

1. A method for manufacturing a color filter on array (COA) liquid crystal panel, comprising the following steps:
(1) providing an array substrate and a glass substrate,
wherein the array substrate comprises red, green, blue sub pixel zones, each of the sub pixel zones comprising a base plate, a gate terminal and a scan line arranged on the base plate, a gate insulation layer arranged on the gate terminal and covering the base plate, a semiconductor layer arranged on the gate insulation layer and corresponding to the gate terminal, source/drain terminals arranged on the gate insulation layer and respectively in connection with two ends of the semiconductor layer, a signal line arranged on the gate insulation layer and perpendicularly intersecting the scan line in a horizontal direction, and a passivation layer arranged on the source/drain terminals and covering the gate insulation layer;
(2) forming a color resist layer on the passivation layer,
wherein the color resist layer comprises red, green, blue color resist blocks formed to respectively correspond to the red, green, blue sub pixel zones, two of the color resist blocks that are arranged adjacent to each other in a lateral direction forming a first intersection zone therebetween, the first intersection zone being located above the signal line, two of the color resist blocks that are arranged adjacent to each other in a longitudinal direction forming a second intersection zone therebetween, the second intersection zone being located above the scan line;
(3) forming a first via in the color resist layer to correspond to and be located above the source/drain terminals and forming a first pixel electrode layer on the color resist layer,
wherein the first pixel electrode layer is set in engagement with the source/drain terminals through the first via;
(4) forming a planarization layer on the first pixel electrode layer and forming a second via in the planarization layer;
(5) depositing and patterning a second pixel electrode layer on the planarization layer,
wherein the second pixel electrode layer is set in engagement with the first pixel electrode layer through the second via, the second pixel electrode layer comprising a pixel electrode block located in each of the sub pixel zones, the pixel electrode block having a lateral border located above the scan line and a longitudinal border located above the signal line;
(6) forming a dot-like black matrix on the glass substrate at a location corresponding to the semiconductor layer and forming a common electrode layer on the black matrix; and
(7) laminating the array substrate and the glass substrate with each other and filling therein a liquid crystal layer.

2. The method for manufacturing the COA liquid crystal panel as claimed in claim 1 , wherein step (2) uses a coating process to form the color resist layer.

3. The method for manufacturing the COA liquid crystal panel as claimed in claim 1 , wherein step (4) uses an exposure process to form the second via and the planarization layer is formed of a transparent organic material.

4. The method for manufacturing the COA liquid crystal panel as claimed in claim 1 , wherein step (5) uses physical vapor deposition to form the second pixel electrode layer.

5. The method for manufacturing the COA liquid crystal panel as claimed in claim 1 , wherein the first pixel electrode layer, the second pixel electrode layer, and the common electrode layer are made of a material of indium tin oxide.

6. A color filter on array (COA) liquid crystal panel, comprising an array substrate, a glass substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the glass substrate;
wherein the array substrate comprises red, green, blue sub pixel zones, each of the sub pixel zones comprising a base plate, a gate terminal and a scan line arranged on the base plate, a gate insulation layer arranged on the gate terminal and covering the base plate, a semiconductor layer arranged on the gate insulation layer and corresponding to the gate terminal, source/drain terminals arranged on the gate insulation layer and respectively in connection with two ends of the semiconductor layer, a signal line arranged on the gate insulation layer and perpendicularly intersecting the scan line in a horizontal direction, a passivation layer arranged on the source/drain terminals and covering the gate insulation layer, a color resist layer arranged on the passivation layer, a first pixel electrode layer arranged on the color resist layer, a planarization layer arranged on the first pixel electrode layer, and a second pixel electrode layer arranged on the planarization layer;
the color resist layer and the passivation layer comprise a first via formed therein to correspond to and be located above the source/drain terminals, the planarization layer comprising a second via formed therein, the first pixel electrode layer being in engagement with the source/drain terminals through the first via, the second pixel electrode layer being in engagement with the first pixel electrode layer through the second via; and
the color resist layer comprises red, green, blue color resist blocks formed to respectively correspond to the red, green, blue sub pixel zones, two of the color resist blocks that are arranged adjacent to each other in a lateral direction forming a first intersection zone therebetween, the first intersection zone being located above the signal line, two of the color resist blocks that are arranged adjacent to each other in a longitudinal direction forming a second intersection zone therebetween, the second intersection zone being located above the scan line, the second pixel electrode layer comprising a pixel electrode block located in each of the sub pixel zones, the pixel electrode block having a lateral border located above the scan line and a longitudinal border located above the signal line.

7. The COA liquid crystal panel as claimed in claim 6 , wherein the planarization layer is formed of a transparent organic material.

8. The COA liquid crystal panel as claimed in claim 6 , wherein the glass substrate comprises a dot-like black matrix formed thereon at a location corresponding to the semiconductor layer and a common electrode layer is formed on the black matrix.

9. The COA liquid crystal panel as claimed in claim 8 , wherein the first pixel electrode layer, the second pixel electrode layer, and the common electrode layer are formed of a material of indium tin oxide.

10. The COA liquid crystal panel as claimed in claim 6 , wherein the source/drain terminals, the gate terminal, the scan line, and the signal line are made of metallic materials of iron, molybdenum, or copper.

11. A color filter on array (COA) liquid crystal panel, comprising an array substrate, a glass substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the glass substrate;
wherein the array substrate comprises red, green, blue sub pixel zones, each of the sub pixel zones comprising a base plate, a gate terminal and a scan line arranged on the base plate, a gate insulation layer arranged on the gate terminal and covering the base plate, a semiconductor layer arranged on the gate insulation layer and corresponding to the gate terminal, source/drain terminals arranged on the gate insulation layer and respectively in connection with two ends of the semiconductor layer, a signal line arranged on the gate insulation layer and perpendicularly intersecting the scan line in a horizontal direction, a passivation layer arranged on the source/drain terminals and covering the gate insulation laye

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelectrics Tech Co Ltd

Inventors

• Xu Hongyuan
• Sun Bo

Classifications

• G02F2201/123

  pixel · CPC title

• G02F2001/136295

  Physics · mapped topic

• G02F1/13439

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title

• G02F2001/136222

  Physics · mapped topic

• G02F2001/133302

  Physics · mapped topic