Frequency-domain high-speed bus signal integrity compliance model

Patent metadata

Field	Value
Publication number	US-9638750-B2
Application number	US-201514721788-A
Country	US
Kind code	B2
Filing date	May 26, 2015
Priority date	May 26, 2015
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

Embodiments of the present disclosure provide apparatus for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The apparatus includes at least one processor and a memory coupled to the at least one processor. The processor is configured to: identify at least one design criteria; obtain boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria; and verify whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

First claim

What is claimed is:

1. A computer program product for channel compliance testing, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to,
identify at least one design criteria;
obtain boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria; and
verify whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels, wherein the signal channel is part of communication bus and the boundary sets of frequency domain parameters comprise at least one parameter related to insertion loss and at least one parameter related to a crosstalk ratio at a fundamental frequency of the bus.

2. The computer program product of claim 1 , wherein the program instructions are executable by the processor to further cause the processor to derive the frequency domain parameters for the particular channel from S-parameters indicative of a frequency response of the particular channel.

3. The computer program product of claim 1 , wherein the design criteria comprises a desired bit error rate for a particular set of bus transmitter and receiver properties.

4. The computer program product of claim 1 , wherein the program instructions are executable by the processor to further cause the processor to determine the boundary sets using a genetic.

5. The computer program product of claim 1 , wherein the particular signal channel is used for communication between a first and second components and the boundary sets are determined for at least one known property of the first and second components.

6. The computer program product of claim 1 , wherein the verifying comprises:
determining whether the particular signal channel is compliant based on a comparison of the frequency domain parameters for the particular channel to frequency domain parameters of a first boundary set; and
if not, determining whether the particular signal channel is compliant based on a comparison of the frequency domain parameters for the particular channel to frequency domain parameters of a second boundary set.

7. A processing system, comprising:
at least one processor configured to:
identify at least one design criteria;
obtain boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria; and
verify whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels, wherein the signal channel is part of a communication bus and the boundary sets of frequency domain parameters comprise at least one parameter related to insertion loss and at least one parameter related to a crosstalk ratio at a fundamental frequency of the bus; and

a memory coupled to the at least one processor.

8. The processing system of claim 7 , wherein the processor is configured to derive the frequency domain parameters for the particular channel from S-parameters indicative of a frequency response of the particular channel.

9. The processing system of claim 7 , wherein the design criteria comprises a desired bit error rate for a particular set of bus transmitter and receiver properties.

10. The processing system of claim 7 , wherein the processor is configured to determine the boundary sets using a genetic algorithm.

11. The processing system of claim 7 , wherein the particular signal channel is used for communication between a first and second components and the boundary sets are determined for at least one known property of the first and second components.

Assignees

• IBM

Inventors

• Becker Wiren D
• Dreps Daniel M
• Hejase Jose A
• Wiedemeier Glen A
• Win Si T

Classifications

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/31703 Primary

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title