Electronic device, electronic apparatus, method of manufacturing base substrate, and method of manufacturing electronic device

US9635769B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9635769-B2
Application numberUS-201313858279-A
CountryUS
Kind codeB2
Filing dateApr 8, 2013
Priority dateApr 10, 2012
Publication dateApr 25, 2017
Grant dateApr 25, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic device has a package and a piezoelectric element accommodated in an accommodating space formed inside the package. The package has a frame-like metallization layer bonding a base substrate and a lid together and electrodes formed on and in the base substrate and electrically connected with the piezoelectric element. The metallization layer is insulated from the electrodes.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic device comprising: an electronic component; a base substrate to which the electronic component is fixed; a lid portion accommodating the electronic component in a space arranged together with the base substrate; a frame-like metallization layer arranged above the base substrate and bonding the base substrate and the lid portion together; and an electrode arranged above the base substrate, wherein the metallization layer and the electrode are insulated from each other, the metallization layer has a plurality of metal layers including a first metal layer, a second metal layer, and a third metal layer stacked above the base substrate, the first metal layer has a thermal conductivity that is less than or equal to 50% of a thermal conductivity of the second metal layer, in plan view, a width of the first metal layer that is located closest to the base substrate side is smaller than a width of at least one of the remaining plurality of metal layers, the second metal layer is sandwiched by the first and third metal layers; the third metal layer directly contacts each of the first and second metal layers, end portions of the third metal layer face and directly contact the base substrate, a portion of the third metal layer is located between the second metal layer and the base substrate, and wherein the first metal layer is a Ni—Cr-based alloy. 2. The electronic device according to claim 1 , wherein at least one of the plurality of metal layers includes a material containing as a main component one of gold, silver, and copper. 3. The electronic device according to claim 1 , wherein the electrode has a through-electrode penetrating the base substrate and spaced apart from the metallization layer by at least 150 μm. 4. An electronic apparatus comprising: a casing; and the electronic device according to claim 1 positioned within the casing. 5. A method of manufacturing a base substrate including an electrode formed on one of surfaces, an electrode formed on the other surface and electrically connected with the electrode on the one surface, and a metallization layer formed on the one surface and arranged so as to be insulated from the electrode on the one surface and surround the electrode on the one surface, the method comprising: simultaneously forming the electrode on the one surface and the metallization layer by plating, wherein the metallization layer has a plurality of metal layers including a first metal layer, a second metal layer, and a third metal layer stacked above the base substrate, the first metal layer has a thermal conductivity that is less than or equal to 50% of a thermal conductivity of the second metal layer, in plan view, a width of one of the first metal layer that is located closest to the base substrate side is smaller than a width of at least one of the remaining plurality of metal layers, the second metal layer is sandwiched between the first and third metal layers, the third metal layer directly contacts each of the first and second metal layers, end portions of the third metal layer face and directly contact the base substrate, a portion of the third metal layer is located between the second metal layer and the base substrate, and wherein the first metal layer is a Ni—Cr-based alloy. 6. A method of manufacturing an electronic device, comprising: preparing a lid made of a metal and a base substrate including an electrode formed on one of surfaces, an electrode formed on the other surface and electrically connected with the electrode on the one surface, and a metallization layer formed on the one surface and arranged so as to be insulated from the electrode on the one surface and surround the electrode on the one surface, wherein the metallization layer has a plurality of metal layers including a first metal layer, a second metal layer, and a third metal layer stacked above the base substrate, the first metal layer has a thermal conductivity that is less than or equal to 50% of a thermal conductivity of the second metal layer, in plan view, a width of one of the first metal layer that is located closest to the base substrate side is smaller than a width of at least one of the remaining plurality of metal layers, the second metal layer is sandwiched between the first and third metal layers, the third metal layer directly contacts each of the first and second metal layers, end portions of the third metal layer face and directly contact the base substrate, and a portion of the third metal layer is located between the second metal layer and the base substrate; and bonding the lid and the base substrate together by irradiation with an energy beam, wherein the first metal layer is a Ni—Cr-based alloy.

Assignees

Inventors

Classifications

  • Manufacturing circuit on or in base · CPC title

  • by conductive adhesives · CPC title

  • by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241) · CPC title

  • Shields or metal cases · CPC title

  • in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern · CPC title

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Frequently asked questions

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What does patent US9635769B2 cover?
An electronic device has a package and a piezoelectric element accommodated in an accommodating space formed inside the package. The package has a frame-like metallization layer bonding a base substrate and a lid together and electrodes formed on and in the base substrate and electrically connected with the piezoelectric element. The metallization layer is insulated from the electrodes.
Who is the assignee on this patent?
Seiko Epson Corp
What technology area does this patent fall under?
Primary CPC classification H05K1/111. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 25 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).