Architectures and methods related to insertion loss reduction and improved isolation in switch designs

Patent metadata

Field	Value
Publication number	US-9634718-B2
Application number	US-201514737453-A
Country	US
Kind code	B2
Filing date	Jun 11, 2015
Priority date	Jun 12, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Architectures and methods related to insertion loss reduction and improved isolation in switch designs. In some embodiments, a switching architecture can include a switch network having one or more switchable radio-frequency (RF) signal paths, where each path contributes to a parasitic effect associated with the switch network. The switching architecture can further include a parasitic compensation circuit coupled to a node of the switch network. The parasitic compensation circuit can be configured to compensate for the parasitic effect of the switch network.

First claim

What is claimed is:

1. A switching architecture comprising:
a switch network that includes one or more switchable signal paths coupled to a common node, each switchable signal path including a series arm switch configured to connect the common node and a respective path node in an ON state and disconnect the common node from the respective path node in an OFF state, each switchable signal path further including a shunt arm switch configured to connect the respective path node to a ground when the corresponding series arm switch is in the OFF state and disconnect the respective path node from the ground when the corresponding series arm switch is in the ON state, each switchable signal path contributing to a parasitic effect associated with the switch network; and
a parasitic compensation circuit coupled to the common node and configured to compensate for the parasitic effect of the switch network.

2. The switching architecture of claim 1 wherein the switch network includes a plurality of switchable signal paths.

3. The switching architecture of claim 1 wherein the common node is an antenna port or coupled to the antenna port.

4. The switching architecture of claim 1 wherein each series arm switch includes a stack of transistor devices, each transistor device having an off-capacitance Coff that increases with its size, and each shunt arm switch includes a stack of transistor devices, each transistor device having an off-capacitance Coff that increases with its size.

5. The switching architecture of claim 4 wherein each transistor device of the series arm switch includes N field-effect transistor(s) arranged in a parallel configuration, and each transistor device of the shunt arm switch includes M arranged in a parallel configuration, each of N and M being a positive integer.

6. The switching architecture of claim 4 wherein the parasitic compensation circuit includes an inductive circuit that couples the common node and the ground, the inductive circuit having an inductance of L that compensates for the parasitic effect that includes one or more of the off-capacitances of the series arm switches and the shunt arm switches.

7. The switching architecture of claim 6 wherein the inductance L of the parasitic compensation circuit is selected to have a value of L=1/[4π 2 f 2 (Coff_total)], the quantity f being an operating frequency, the quantity Coff_total being a total off-capacitances of the switch network.

8. The switching architecture of claim 6 wherein the presence of the inductance L of the parasitic compensation circuit allows either or both of the series arm and shunt arm switch transistors to be sized larger to improve switch performance while reducing the parasitic effect of the off-capacitances of the series arm switches and the shunt arm switches.

9. The switching architecture of claim 8 wherein the switch performance includes insertion loss performance.

10. The switching architecture of claim 9 wherein the sizes of either or both of the series arm and shunt arm switch transistors are larger than corresponding transistors of a switching architecture without the inductance L of the parasitic compensation circuit.

11. The switching architecture of claim 10 wherein the switch network of the switching architecture with the inductance L of the parasitic compensation circuit has a lower insertion loss than that of the switching architecture without the inductance L of the parasitic compensation circuit.

12. The switching architecture of claim 8 wherein the switch performance includes isolation performance.

13. The switching architecture of claim 12 wherein the size of the shunt arm switch transistor is larger than a corresponding transistor of a switching architecture without the inductance L of the parasitic compensation circuit.

14. The switching architecture of claim 6 wherein the inductive circuit is configured to provide a substantially fixed value for the inductance of L of the parasitic compensation circuit.

15. The switching architecture of claim 6 wherein the inductive circuit is configured to provide a plurality of different values for the inductance of L of the parasitic compensation circuit.

16. A method for routing signals, the method comprising:
performing a switching operation in a switch network to allow passage of one or more signals through one or more corresponding switchable signal paths coupled to a common node, each switchable signal path including a series arm switch configured to connect the common node and a respective path node in an ON state and disconnect the common node from the respective path node in an OFF state, each switchable signal path further including a shunt arm switch configured to connect the respective path node to a ground when the corresponding series arm switch is in the OFF state and disconnect the respective path node from the ground when the corresponding series arm switch is in the ON state, each switchable signal path contributing to a parasitic effect associated with the switch network; and
compensating for the parasitic effect at the common.

17. A radio-frequency device comprising:
a transceiver configured to process signals;
an antenna switch module in communication with the transceiver and configured to route amplified signals for transmission and received signals for amplification, the antenna switch module including a switch network having one or more switchable signal paths coupled to a common node, each switchable signal path including a series arm switch configured to connect the common node and a respective path node in an ON state and disconnect the common node from the respective path node in an OFF state, each switchable signal path further including a shunt arm switch configured to connect the respective path node to a ground when the corresponding series arm switch is in the OFF state and disconnect the respective path node from the ground when the corresponding series arm switch is in the ON state, each switchable signal path contributing to a parasitic effect associated with the switch network, the antenna switch module further including a parasitic compensation circuit coupled to the common node and configured to compensate for the parasitic effect of the switch network; and
an antenna in communication with the antenna switch module and configured to facilitate either or both of transmission and reception of the respective signals.

Assignees

• Skyworks Solutions Inc

Inventors

• Lee Junhyung

Classifications

• H04B15/00

  Suppression or limitation of noise or interference (by means associated with receiver H04B1/10) · CPC title

• H03K2017/066

  Maximizing the OFF-resistance instead of minimizing the ON-resistance · CPC title

• H03K17/122

  in field-effect transistor switches · CPC title

• H04B1/44 Primary

  Transmit/receive switching · CPC title

• H03K17/063 Primary

  in field-effect transistor switches · CPC title